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axi_ad9144: axi_ad9144_hw.tcl: Disable unused interfaces instead of not creating them 

Currently the axi_ad9144_hw.tcl script does not create interfaces if they
are not used in the current configuration. This has the disadvantage that
the ports belonging to these interfaces are not included in the generated
HDL wrapper. Which will generate a fair bunch of warnings when synthesizing
the HDL.

Instead always generate all interfaces, but disable those that are not used
in the current configuration. This will make sure that the ports belonging
to these interfaces are properly tied-off in the generate wrapper HDL.

This reduces the amount of false positive warnings generated and makes it
easier to spot actual issues.

While we are at it also use a loop to create the interfaces since they all
follow the same pattern.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-31 21:07:12 +02:00
parent 97083a9766
commit 154e40eaaa
1 changed files with 11 additions and 33 deletions
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44
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -77,45 +77,23 @@ set_interface_property if_tx_data dataBitsPerSymbol 128
ad_alt_intf clock dac_clk output 1
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
add_interface_port dac_ch_0 dac_ddata_0 data Input 64
for {set i 0} {$i < 4} {incr i} {
add_interface dac_ch_${i} conduit end
add_interface_port dac_ch_${i} dac_enable_${i} enable Output 1
add_interface_port dac_ch_${i} dac_valid_${i} valid Output 1
add_interface_port dac_ch_${i} dac_ddata_${i} data Input 64
set_interface_property dac_ch_0 associatedClock if_tx_clk
set_interface_property dac_ch_0 associatedReset none
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_enable_1 enable Output 1
add_interface_port dac_ch_1 dac_valid_1 valid Output 1
add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_tx_clk
set_interface_property dac_ch_1 associatedReset none
set_interface_property dac_ch_${i} associatedClock if_tx_clk
set_interface_property dac_ch_${i} associatedReset none
}
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
proc p_axi_ad9144 {} {
set p_pcore_quad_dual_n [get_parameter_value "QUAD_OR_DUAL_N"]
if {[get_parameter_value QUAD_OR_DUAL_N] == 1} {
add_interface dac_ch_2 conduit end
add_interface_port dac_ch_2 dac_enable_2 enable Output 1
add_interface_port dac_ch_2 dac_valid_2 valid Output 1
add_interface_port dac_ch_2 dac_ddata_2 data Input 64
set_interface_property dac_ch_2 associatedClock if_tx_clk
set_interface_property dac_ch_2 associatedReset none
add_interface dac_ch_3 conduit end
add_interface_port dac_ch_3 dac_enable_3 enable Output 1
add_interface_port dac_ch_3 dac_valid_3 valid Output 1
add_interface_port dac_ch_3 dac_ddata_3 data Input 64
set_interface_property dac_ch_3 associatedClock if_tx_clk
set_interface_property dac_ch_3 associatedReset none
if {[get_parameter_value QUAD_OR_DUAL_N] != 1} {
set_interface_property dac_ch_2 ENABLED false
set_interface_property dac_ch_3 ENABLED false
}
}