tb_base: Fix various test benches

The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.

Delete all the timescale directive from these files.

library/axi_dmac/tb/tb_base.v

@@ -33,8 +33,6 @@
 // ***************************************************************************
 // ***************************************************************************
 
-`timescale 1ns/100ps
-
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;
   reg trigger_reset = 1'b0;

library/jesd204/tb/tb_base.v

@@ -42,8 +42,6 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
-`timescale 1ns/100ps
-
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;
   reg trigger_reset = 1'b0;

library/util_pack/tb/tb_base.v

@@ -33,8 +33,6 @@
 // ***************************************************************************
 // ***************************************************************************
 
-`timescale 1ns/100ps
-
   reg clk = 1'b1;
   reg [3:0] reset_shift = 4'b1111;
   reg trigger_reset = 1'b0;