diff --git a/projects/ad9081_fmca_ebz/a10soc/system_project.tcl b/projects/ad9081_fmca_ebz/a10soc/system_project.tcl index b997b00cc..34bab33d7 100755 --- a/projects/ad9081_fmca_ebz/a10soc/system_project.tcl +++ b/projects/ad9081_fmca_ebz/a10soc/system_project.tcl @@ -8,16 +8,16 @@ source ../../scripts/adi_project_intel.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_RATE=10 TX_RATE=10 RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=16 -# make RX_RATE=2.5 TX_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 -# make RX_RATE=10 TX_RATE=10 RX_JESD_L=2 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=12 TX_JESD_L=2 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=12 +# make RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=16 +# make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 +# make RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_L=2 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=12 TX_JESD_L=2 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=12 # # Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L # Parameter description: # -# RX_RATE : Lane rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Lane rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Lane rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_S : Number of samples per frame @@ -27,18 +27,18 @@ source ../../scripts/adi_project_intel.tcl # adi_project ad9081_fmca_ebz_a10soc [list \ - RX_LANE_RATE [get_env_param RX_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \ ] diff --git a/projects/ad9081_fmca_ebz/vck190/system_project.tcl b/projects/ad9081_fmca_ebz/vck190/system_project.tcl index fa2a3c02b..a2f081fd1 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_project.tcl +++ b/projects/ad9081_fmca_ebz/vck190/system_project.tcl @@ -18,8 +18,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer # 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) # REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link @@ -29,23 +29,23 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M) # -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 adi_project ad9081_fmca_ebz_vck190 0 [list \ - JESD_MODE [get_env_param JESD_MODE 64B66B ]\ - RX_LANE_RATE [get_env_param RX_RATE 11.88 ] \ - TX_LANE_RATE [get_env_param TX_RATE 11.88 ] \ - REF_CLK_RATE [get_env_param REF_CLK_RATE 360 ] \ - RX_JESD_M [get_env_param RX_JESD_M 2 ] \ - RX_JESD_L [get_env_param RX_JESD_L 2 ] \ - RX_JESD_S [get_env_param RX_JESD_S 4 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 12] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 2 ] \ - TX_JESD_L [get_env_param TX_JESD_L 2 ] \ - TX_JESD_S [get_env_param TX_JESD_S 2 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 12] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + JESD_MODE [get_env_param JESD_MODE 64B66B ]\ + RX_LANE_RATE [get_env_param RX_LANE_RATE 11.88 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 11.88 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 360 ] \ + RX_JESD_M [get_env_param RX_JESD_M 2 ] \ + RX_JESD_L [get_env_param RX_JESD_L 2 ] \ + RX_JESD_S [get_env_param RX_JESD_S 4 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 12 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 2 ] \ + TX_JESD_L [get_env_param TX_JESD_L 2 ] \ + TX_JESD_S [get_env_param TX_JESD_S 2 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 12 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ ] diff --git a/projects/ad9081_fmca_ebz/vcu118/system_project.tcl b/projects/ad9081_fmca_ebz/vcu118/system_project.tcl index d96a07884..d0cd6f8eb 100644 --- a/projects/ad9081_fmca_ebz/vcu118/system_project.tcl +++ b/projects/ad9081_fmca_ebz/vcu118/system_project.tcl @@ -9,11 +9,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 -# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_LANE_RATE=16.22016 TX_LANE_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_LANE_RATE=16.50 TX_LANE_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=64B66B RX_LANE_RATE=16.50 TX_LANE_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 # make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 # @@ -22,8 +22,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C # 8B10B - 8b10b link layer defined in JESD 204B # -# RX_RATE : Lane rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Lane rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Lane rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_S : Number of samples per frame @@ -33,19 +33,19 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # adi_project ad9081_fmca_ebz_vcu118 0 [list \ - JESD_MODE [get_env_param JESD_MODE 8B10B ] \ - RX_LANE_RATE [get_env_param RX_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ ] diff --git a/projects/ad9081_fmca_ebz/vcu128/system_project.tcl b/projects/ad9081_fmca_ebz/vcu128/system_project.tcl index 5190df7ac..6e8da8af9 100644 --- a/projects/ad9081_fmca_ebz/vcu128/system_project.tcl +++ b/projects/ad9081_fmca_ebz/vcu128/system_project.tcl @@ -9,11 +9,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 -# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_LANE_RATE=16.22016 TX_LANE_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_LANE_RATE=16.50 TX_LANE_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=64B66B RX_LANE_RATE=16.50 TX_LANE_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 # make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 # @@ -22,8 +22,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C # 8B10B - 8b10b link layer defined in JESD 204B # -# RX_RATE : Lane rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Lane rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Lane rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_S : Number of samples per frame @@ -33,23 +33,23 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # adi_project ad9081_fmca_ebz_vcu128 0 [list \ - JESD_MODE [get_env_param JESD_MODE 8B10B ] \ - RX_LANE_RATE [get_env_param RX_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 16384 ] \ TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16384 ] \ - ADC_DO_MEM_TYPE [get_env_param ADC_DO_MEM_TYPE 2 ] \ - DAC_DO_MEM_TYPE [get_env_param DAC_DO_MEM_TYPE 2 ] \ + ADC_DO_MEM_TYPE [get_env_param ADC_DO_MEM_TYPE 2 ] \ + DAC_DO_MEM_TYPE [get_env_param DAC_DO_MEM_TYPE 2 ] \ ] adi_project_files ad9081_fmca_ebz_vcu128 [list \ diff --git a/projects/ad9081_fmca_ebz/zc706/system_project.tcl b/projects/ad9081_fmca_ebz/zc706/system_project.tcl index a8926f790..3e67ac469 100644 --- a/projects/ad9081_fmca_ebz/zc706/system_project.tcl +++ b/projects/ad9081_fmca_ebz/zc706/system_project.tcl @@ -18,31 +18,31 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer # 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample # [RX/TX]_NUM_LINKS : Number of links # -# +# # !!! For this carrier only 8B10B mode is supported !!! # adi_project ad9081_fmca_ebz_zc706 0 [list \ JESD_MODE 8B10B \ - RX_LANE_RATE [get_env_param RX_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ ] adi_project_files ad9081_fmca_ebz_zc706 [list \ diff --git a/projects/ad9081_fmca_ebz/zcu102/system_project.tcl b/projects/ad9081_fmca_ebz/zcu102/system_project.tcl index aeb1028b5..1e0f27714 100644 --- a/projects/ad9081_fmca_ebz/zcu102/system_project.tcl +++ b/projects/ad9081_fmca_ebz/zcu102/system_project.tcl @@ -18,8 +18,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer # 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported @@ -29,22 +29,22 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project ad9081_fmca_ebz_zcu102 0 [list \ JESD_MODE [get_env_param JESD_MODE 8B10B ] \ - RX_LANE_RATE [get_env_param RX_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {} ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ - TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ - TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \ - SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {} ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ + TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \ + SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \ ] adi_project_files ad9081_fmca_ebz_zcu102 [list \ diff --git a/projects/ad9082_fmca_ebz/vcu118/system_project.tcl b/projects/ad9082_fmca_ebz/vcu118/system_project.tcl index d3cc5b235..b9e7cf61e 100644 --- a/projects/ad9082_fmca_ebz/vcu118/system_project.tcl +++ b/projects/ad9082_fmca_ebz/vcu118/system_project.tcl @@ -9,8 +9,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_LANE_RATE=16.22016 TX_LANE_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 # make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 # @@ -19,8 +19,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer # 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_S : Number of samples per frame @@ -30,19 +30,19 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # adi_project ad9082_fmca_ebz_vcu118 0 [list \ - JESD_MODE [get_env_param JESD_MODE 8B10B ] \ - RX_LANE_RATE [get_env_param RX_RATE 15 ] \ - TX_LANE_RATE [get_env_param TX_RATE 15 ] \ - RX_JESD_M [get_env_param RX_JESD_M 4 ] \ - RX_JESD_L [get_env_param RX_JESD_L 8 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 4 ] \ - TX_JESD_L [get_env_param TX_JESD_L 8 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 15 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 15 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ ] diff --git a/projects/ad9082_fmca_ebz/zc706/system_project.tcl b/projects/ad9082_fmca_ebz/zc706/system_project.tcl index 624f403ae..e3d4d2b64 100644 --- a/projects/ad9082_fmca_ebz/zc706/system_project.tcl +++ b/projects/ad9082_fmca_ebz/zc706/system_project.tcl @@ -17,31 +17,31 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C # 8B10B - 8b10b link layer defined in JESD 204B # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported # [RX/TX]_NUM_LINKS : Number of links # -# +# # !!! For this carrier only 8B10B mode is supported !!! # adi_project ad9082_fmca_ebz_zc706 0 [list \ - JESD_MODE 8B10B \ - RX_LANE_RATE [get_env_param RX_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + JESD_MODE 8B10B \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ ] adi_project_files ad9082_fmca_ebz_zc706 [list \ diff --git a/projects/ad9082_fmca_ebz/zcu102/system_project.tcl b/projects/ad9082_fmca_ebz/zcu102/system_project.tcl index 7e9df5cd5..2e9f665f3 100644 --- a/projects/ad9082_fmca_ebz/zcu102/system_project.tcl +++ b/projects/ad9082_fmca_ebz/zcu102/system_project.tcl @@ -18,8 +18,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 64B66B - 64b66b link layer defined in JESD 204C # 8B10B - 8b10b link layer defined in JESD 204B # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported @@ -30,21 +30,21 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # adi_project ad9082_fmca_ebz_zcu102 0 [list \ - JESD_MODE [get_env_param JESD_MODE 8B10B ]\ - RX_LANE_RATE [get_env_param RX_RATE 15 ] \ - TX_LANE_RATE [get_env_param TX_RATE 15 ] \ - RX_JESD_M [get_env_param RX_JESD_M 4 ] \ - RX_JESD_L [get_env_param RX_JESD_L 8 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {}] \ - TX_JESD_M [get_env_param TX_JESD_M 4 ] \ - TX_JESD_L [get_env_param TX_JESD_L 8 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ - TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {}] \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 15 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 15 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {}] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {}] \ ] adi_project_files ad9082_fmca_ebz_zcu102 [list \ diff --git a/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl b/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl index 035565771..05c0257f3 100644 --- a/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl +++ b/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl @@ -137,8 +137,8 @@ ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in # Common PHYs # Use two instances since they are located on different SLRS -set rx_rate $ad_project_params(RX_RATE) -set tx_rate $ad_project_params(TX_RATE) +set rx_rate $ad_project_params(RX_LANE_RATE) +set tx_rate $ad_project_params(TX_LANE_RATE) set ref_clk_rate $ad_project_params(REF_CLK_RATE) ad_ip_instance jesd204_phy jesd204_phy_121_122 [list \ diff --git a/projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl b/projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl index bd6544aa0..a815c938a 100644 --- a/projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl +++ b/projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl @@ -7,22 +7,22 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # other case returns the default value specified in its second parameter field. # # How to use over-writable parameters from the environment: -# +# # e.g. # make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 -# make JESD_MODE=64B66B RX_JESD_L=2 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=16 -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 REF_CLK_RATE=250 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 RX_PLL_SEL=1 TX_PLL_SEL=1 +# make JESD_MODE=64B66B RX_JESD_L=2 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=16 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 REF_CLK_RATE=250 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 RX_PLL_SEL=1 TX_PLL_SEL=1 # -# RX_RATE,TX_RATE,REF_CLK_RATE used only in 64B66B mode +# RX_LANE_RATE,TX_LANE_RATE,REF_CLK_RATE used only in 64B66B mode # # Parameter description: -# JESD_MODE : used link layer encoder mode +# JESD_MODE : used link layer encoder mode # 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer # 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer -# -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode -# [RX/TX]_PLL_SEL : used in 64B66B mode, +# +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode +# [RX/TX]_PLL_SEL : used in 64B66B mode, # 0 - CPLL for lane rates 4-12.5 Gbps and integer sub-multiples # 1 - QPLL0 for lane rates 19.6–32.75 Gbps and integer sub-multiples (e.g. 9.8–16.375;) # 2 - QPLL1 for lane rates 16.0–26.0 Gbps and integer sub-multiple (e.g. 8.0–13.0;) @@ -37,25 +37,25 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # adi_project ad_quadmxfe1_ebz_vcu118 0 [list \ - JESD_MODE [get_env_param JESD_MODE 64B66B ] \ - RX_RATE [get_env_param RX_RATE 16.5 ] \ - TX_RATE [get_env_param TX_RATE 16.5 ] \ - RX_PLL_SEL [get_env_param RX_PLL_SEL 2 ] \ - TX_PLL_SEL [get_env_param TX_PLL_SEL 2 ] \ - REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 2 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 4 ] \ - TX_JESD_M [get_env_param TX_JESD_M 16 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 4 ] \ - RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ - TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16 ] \ - DAC_TPL_XBAR_ENABLE [get_env_param DAC_TPL_XBAR_ENABLE 0 ] \ + JESD_MODE [get_env_param JESD_MODE 64B66B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 16.5 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 16.5 ] \ + RX_PLL_SEL [get_env_param RX_PLL_SEL 2 ] \ + TX_PLL_SEL [get_env_param TX_PLL_SEL 2 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 2 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 4 ] \ + TX_JESD_M [get_env_param TX_JESD_M 16 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 4 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16 ] \ + DAC_TPL_XBAR_ENABLE [get_env_param DAC_TPL_XBAR_ENABLE 0 ] \ ] adi_project_files ad_quadmxfe1_ebz_vcu118 [list \