library/common/util_pulse_gen: Fix for unupdateable registers
- Fixed an issue where if Pulse Period is set to 0, the load_config won't work Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>main
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15e9c65c83
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -62,14 +62,23 @@ module util_pulse_gen #(
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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if (rstn == 1'b0) begin
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pulse_period_d <= PULSE_PERIOD;
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if (PULSE_PERIOD == 'd0) begin
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pulse_period_d <= 32'h1;
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pulse_period_read <= 32'h1;
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end else begin
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pulse_period_d <= PULSE_PERIOD;
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pulse_period_read <= PULSE_PERIOD;
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end
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pulse_width_d <= PULSE_WIDTH;
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pulse_width_d <= PULSE_WIDTH;
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pulse_period_read <= PULSE_PERIOD;
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pulse_width_read <= PULSE_WIDTH;
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pulse_width_read <= PULSE_WIDTH;
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end else begin
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end else begin
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// latch the input period/width values
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// latch the input period/width values
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if (load_config) begin
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if (load_config) begin
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pulse_period_read <= pulse_period;
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if (pulse_period == 'd0) begin
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pulse_period_read <= 32'h1;
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end else begin
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pulse_period_read <= pulse_period;
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end
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pulse_width_read <= pulse_width;
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pulse_width_read <= pulse_width;
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end
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end
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// update the current period/width at the end of the period
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// update the current period/width at the end of the period
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