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library/common/util_pulse_gen: Fix for unupdateable registers 

- Fixed an issue where if Pulse Period is set to 0, the load_config won't work

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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Istvan-Zsolt Szekely 2023-02-01 11:43:18 +02:00 committed by IstvanZsSzekely
parent db94628cc6
commit 15e9c65c83
1 changed files with 13 additions and 4 deletions
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13
library/common/util_pulse_gen.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -62,14 +62,23 @@ module util_pulse_gen #(
always @(posedge clk) begin
if (rstn == 1'b0) begin
if (PULSE_PERIOD == 'd0) begin
pulse_period_d <= 32'h1;
pulse_period_read <= 32'h1;
end else begin
pulse_period_d <= PULSE_PERIOD;
pulse_width_d <= PULSE_WIDTH;
pulse_period_read <= PULSE_PERIOD;
end
pulse_width_d <= PULSE_WIDTH;
pulse_width_read <= PULSE_WIDTH;
end else begin
// latch the input period/width values
if (load_config) begin
if (pulse_period == 'd0) begin
pulse_period_read <= 32'h1;
end else begin
pulse_period_read <= pulse_period;
end
pulse_width_read <= pulse_width;
end
// update the current period/width at the end of the period