From 1613f7fb4148c3bf10ec8d99c69da56b60df7d35 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 23 Feb 2015 17:20:12 +0200 Subject: [PATCH] cftl_cip: Add util_pmod_fmeter IP to library Frequency meter IP for CN0332. --- library/common/up_pmod.v | 161 ++++++++++++++++ library/util_pmod_fmeter/util_pmod_fmeter.v | 177 ++++++++++++++++++ .../util_pmod_fmeter/util_pmod_fmeter_core.v | 83 ++++++++ .../util_pmod_fmeter/util_pmod_fmeter_ip.tcl | 18 ++ projects/cftl_cip/common/cftl_cip_bd.tcl | 4 +- 5 files changed, 441 insertions(+), 2 deletions(-) create mode 100644 library/common/up_pmod.v create mode 100644 library/util_pmod_fmeter/util_pmod_fmeter.v create mode 100644 library/util_pmod_fmeter/util_pmod_fmeter_core.v create mode 100644 library/util_pmod_fmeter/util_pmod_fmeter_ip.tcl diff --git a/library/common/up_pmod.v b/library/common/up_pmod.v new file mode 100644 index 000000000..e20b07565 --- /dev/null +++ b/library/common/up_pmod.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_pmod ( + + pmod_clk, + pmod_rst, + pmod_signal_freq, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + localparam PCORE_VERSION = 32'h00010001; + parameter PCORE_ID = 0; + + input pmod_clk; + output pmod_rst; + input [31:0] pmod_signal_freq; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal signals + + wire [31:0] up_pmod_signal_freq_s; + wire up_wreq_s; + wire up_rreq_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; + assign up_preset_s = ~up_resetn; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_resetn <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin + up_resetn <= up_wdata[0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= PCORE_ID; + 8'h02: up_rdata <= up_scratch; + 8'h03: up_rdata <= up_pmod_signal_freq_s; + 8'h10: up_rdata <= up_resetn; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // resets + + ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(pmod_clk), .rst(pmod_rst)); + + // adc control & status + + up_xfer_status #(.DATA_WIDTH(32)) i_pmod_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status (up_pmod_signal_freq_s), + .d_rst (pmod_rst), + .d_clk (pmod_clk), + .d_data_status (pmod_signal_freq)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/util_pmod_fmeter/util_pmod_fmeter.v b/library/util_pmod_fmeter/util_pmod_fmeter.v new file mode 100644 index 000000000..0ea1732ba --- /dev/null +++ b/library/util_pmod_fmeter/util_pmod_fmeter.v @@ -0,0 +1,177 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +module util_pmod_fmeter ( + + ref_clk, + square_signal, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + // parameters + + parameter PCORE_ID = 0; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // physical interface + + input ref_clk; + input square_signal; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal signals + + wire up_clk; + wire up_rstn; + wire reset; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + + wire [31:0] signal_freq_s; + + //defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid = 1'b1; + + // frequency measurment module + + util_pmod_fmeter_core i_util_pmod_fmeter_core ( + .ref_clk(ref_clk), + .reset(reset), + .square_signal(square_signal), + .signal_freq(signal_freq_s)); + + // register map + + up_pmod i_up_pmod( + .pmod_clk(ref_clk), + .pmod_rst(reset), + .pmod_signal_freq(signal_freq_s), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_s), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_s), + .up_rack(up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/library/util_pmod_fmeter/util_pmod_fmeter_core.v b/library/util_pmod_fmeter/util_pmod_fmeter_core.v new file mode 100644 index 000000000..92285da80 --- /dev/null +++ b/library/util_pmod_fmeter/util_pmod_fmeter_core.v @@ -0,0 +1,83 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +module util_pmod_fmeter_core ( + ref_clk, + reset, + square_signal, + signal_freq); + + input ref_clk; + input reset; + input square_signal; + output [31:0] signal_freq; + + // registers + + reg [31:0] signal_freq = 'h0; + reg [31:0] signal_freq_counter = 'h0; + reg [ 2:0] square_signal_buf = 'h0; + + wire signal_freq_en; + + assign signal_freq_en = ~square_signal_buf[2] & square_signal_buf[1]; + + // internal signals + + always @(posedge ref_clk) begin + square_signal_buf[0] <= square_signal; + square_signal_buf[2:1] <= square_signal_buf[1:0]; + end + + always @(posedge ref_clk) begin + if (reset == 1'b1) begin + signal_freq <= 32'b0; + signal_freq_counter <= 32'b0; + end else begin + if(signal_freq_en == 1'b1) begin + signal_freq <= signal_freq_counter; + signal_freq_counter <= 32'h0; + end else begin + signal_freq_counter <= signal_freq_counter + 32'h1; + end + end + end + +endmodule + diff --git a/library/util_pmod_fmeter/util_pmod_fmeter_ip.tcl b/library/util_pmod_fmeter/util_pmod_fmeter_ip.tcl new file mode 100644 index 000000000..ced6fb434 --- /dev/null +++ b/library/util_pmod_fmeter/util_pmod_fmeter_ip.tcl @@ -0,0 +1,18 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_pmod_fmeter +adi_ip_files util_pmod_fmeter [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_pmod.v" \ + "util_pmod_fmeter.v" \ + "util_pmod_fmeter_core.v"] + +adi_ip_properties util_pmod_fmeter + +ipx::save_core [ipx::current_core] + diff --git a/projects/cftl_cip/common/cftl_cip_bd.tcl b/projects/cftl_cip/common/cftl_cip_bd.tcl index 51cdbae13..91f5b5494 100644 --- a/projects/cftl_cip/common/cftl_cip_bd.tcl +++ b/projects/cftl_cip/common/cftl_cip_bd.tcl @@ -11,7 +11,7 @@ set pmod_gpio [create_bd_port -dir I pmod_gpio] # interrupts - set pmod_spi_dma_intr [create_bd_port -dir O pmod_spi_dma_intr] + set pmod_spi_dma_intr [create_bd_port -dir O pmod_spi_dma_intr] # instances @@ -35,7 +35,7 @@ set pmod_spi_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 pmod_spi_dma_interconnect] set_property -dict [list CONFIG.NUM_MI {1}] $pmod_spi_dma_interconnect - set pmod_gpio_core [create_bd_cell -type ip -vlnv analog.com:user:util_pmod_ss:1.0 pmod_gpio_core] + set pmod_gpio_core [create_bd_cell -type ip -vlnv analog.com:user:util_pmod_fmeter:1.0 pmod_gpio_core] # additional configurations set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7