ad_ip_jesd204_tpl_dac: Add support for modes with N or N' != 16
The ad_ip_jesd204_tpl_dac currently only supports JESD204 modes that have both N and N' set to 16. Newer DACs like the AD9172 support modes where N and N' are not equal to 16. Add support for these modes. The width of the internal channel data path is set to N, only processing as many bits as necessary. At the framer the data is up-sized to N' bits with tail bits inserted as necessary. This data is then passed to the link layer. The width at the DMA interface is kept at 16 bits per sample regardless of the configuration of either N or N'. This is done to keep the interface consistent with the existing infrastructure it will connect to like upack and DMA. The data is expected to the LSB aligned, the unused MSBs will be ignored. Same is true for the test-pattern data registers. These register keep their existing 16-bit layout, but unused MSBs will be ignored by the core. The PN generators are modified to create only N bits of data per sample. Note that while the core can now support modes with N' = 12 there is still the restriction that requires the number of frames per beat to be an even number. Which means that not all modes with N' = 12 can be supported yet. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
István Csomortáni
parent
a98bc88b84
commit
169f38e7d1
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@ -132,6 +132,8 @@ module axi_ad9144 #(
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.ID (ID),
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.NUM_LANES (NUM_CHANNELS * 2),
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.NUM_CHANNELS (NUM_CHANNELS),
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.CONVERTER_RESOLUTION (16),
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.BITS_PER_SAMPLE (16),
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.SAMPLES_PER_FRAME (1),
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.DDS_TYPE (DAC_DDS_TYPE),
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.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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@ -92,6 +92,8 @@ module axi_ad9152 #(
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.ID(ID),
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.NUM_LANES(4),
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.NUM_CHANNELS(2),
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.CONVERTER_RESOLUTION (16),
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.BITS_PER_SAMPLE (16),
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.SAMPLES_PER_FRAME (1),
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.DDS_TYPE (DAC_DDS_TYPE),
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.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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@ -28,6 +28,8 @@ module ad_ip_jesd204_tpl_dac #(
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parameter NUM_LANES = 4,
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parameter NUM_CHANNELS = 2,
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parameter SAMPLES_PER_FRAME = 1,
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parameter CONVERTER_RESOLUTION = 16,
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parameter BITS_PER_SAMPLE = 16,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DDS_CORDIC_PHASE_DW = 16,
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@ -81,8 +83,9 @@ module ad_ip_jesd204_tpl_dac #(
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/* Static for now */
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localparam OCTETS_PER_BEAT = 4;
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localparam DATA_PATH_WIDTH = 2 * OCTETS_PER_BEAT * NUM_LANES / NUM_CHANNELS;
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localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
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localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
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localparam DMA_DATA_WIDTH = 16 * DATA_PATH_WIDTH * NUM_CHANNELS;
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// internal signals
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@ -157,6 +160,7 @@ module ad_ip_jesd204_tpl_dac #(
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.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.DDS_TYPE (DDS_TYPE),
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.DDS_CORDIC_DW (DDS_CORDIC_DW),
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.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW)
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@ -26,6 +26,7 @@
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module ad_ip_jesd204_tpl_dac_channel #(
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parameter DATAPATH_DISABLE = 0,
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parameter DATA_PATH_WIDTH = 4,
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parameter CONVERTER_RESOLUTION = 16,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DDS_CORDIC_PHASE_DW = 16
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@ -35,12 +36,12 @@ module ad_ip_jesd204_tpl_dac_channel #(
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input clk,
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input [DATA_PATH_WIDTH*16-1:0] dma_data,
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output reg [DATA_PATH_WIDTH*16-1:0] dac_data = 'h00,
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output reg [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] dac_data = 'h00,
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// PN data
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input [DATA_PATH_WIDTH*16-1:0] pn7_data,
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input [DATA_PATH_WIDTH*16-1:0] pn15_data,
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input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
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input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data,
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// Configuration
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@ -62,14 +63,18 @@ module ad_ip_jesd204_tpl_dac_channel #(
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output reg dac_enable = 1'b0
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);
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localparam CR = CONVERTER_RESOLUTION;
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localparam CHANNEL_DATA_WIDTH = DATA_PATH_WIDTH * CR;
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// internal signals
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wire [DATA_PATH_WIDTH*16-1:0] dac_dds_data_s;
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wire [DATA_PATH_WIDTH*16-1:0] dac_pat_data_s;
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wire [CHANNEL_DATA_WIDTH-1:0] dac_dds_data_s;
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wire [CHANNEL_DATA_WIDTH-1:0] dac_dma_data_s;
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wire [CHANNEL_DATA_WIDTH-1:0] dac_pat_data_s;
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generate
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if (DATA_PATH_WIDTH > 1) begin
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assign dac_pat_data_s = {DATA_PATH_WIDTH/2{dac_pat_data_1,dac_pat_data_0}};
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assign dac_pat_data_s = {DATA_PATH_WIDTH/2{dac_pat_data_1[0+:CR],dac_pat_data_0[0+:CR]}};
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end else begin
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reg dac_pat_data_sel = 1'b0;
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@ -82,7 +87,13 @@ module ad_ip_jesd204_tpl_dac_channel #(
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end
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assign dac_pat_data_s = dac_pat_data_sel == 1'b0 ?
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dac_pat_data_0 : dac_pat_data_1;
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dac_pat_data_0[0+:CR] : dac_pat_data_1[0+:CR];
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end
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genvar i;
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/* Data is expected to be LSB aligned, drop unused MSBs */
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for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_dac_dma_data
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assign dac_dma_data_s[CR*i+:CR] = dma_data[16*i+:CR];
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end
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endgenerate
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@ -96,7 +107,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
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4'h5: dac_data <= ~pn15_data;
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4'h4: dac_data <= ~pn7_data;
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4'h3: dac_data <= 'h00;
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4'h2: dac_data <= dma_data;
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4'h2: dac_data <= dac_dma_data_s;
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4'h1: dac_data <= dac_pat_data_s;
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default: dac_data <= dac_dds_data_s;
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endcase
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@ -106,7 +117,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
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ad_dds #(
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.DISABLE (DATAPATH_DISABLE),
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.DDS_DW (16),
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.DDS_DW (CONVERTER_RESOLUTION),
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.PHASE_DW (16),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (DDS_CORDIC_DW),
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@ -27,10 +27,13 @@ module ad_ip_jesd204_tpl_dac_core #(
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parameter DATAPATH_DISABLE = 0,
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parameter NUM_LANES = 1,
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parameter NUM_CHANNELS = 1,
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parameter BITS_PER_SAMPLE = 16,
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parameter CONVERTER_RESOLUTION = 16,
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parameter SAMPLES_PER_FRAME = 1,
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parameter OCTETS_PER_BEAT = 4,
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parameter DATA_PATH_WIDTH = 4,
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parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
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parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * 16 * NUM_CHANNELS,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DDS_CORDIC_PHASE_DW = 16
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@ -44,7 +47,7 @@ module ad_ip_jesd204_tpl_dac_core #(
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// dma interface
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output [NUM_CHANNELS-1:0] dac_valid,
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input [LINK_DATA_WIDTH-1:0] dac_ddata,
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input [DMA_DATA_WIDTH-1:0] dac_ddata,
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// Configuration interface
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@ -66,21 +69,28 @@ module ad_ip_jesd204_tpl_dac_core #(
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output [NUM_CHANNELS-1:0] enable
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);
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localparam DAC_CDW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
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localparam DAC_DATA_WIDTH = DAC_CDW * NUM_CHANNELS;
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localparam DMA_CDW = DATA_PATH_WIDTH * 16;
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assign link_valid = 1'b1;
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wire [LINK_DATA_WIDTH-1:0] dac_data_s;
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wire [DAC_DATA_WIDTH-1:0] dac_data_s;
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wire [DATA_PATH_WIDTH*16-1:0] pn7_data;
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wire [DATA_PATH_WIDTH*16-1:0] pn15_data;
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wire [DAC_CDW-1:0] pn7_data;
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wire [DAC_CDW-1:0] pn15_data;
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// device interface
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ad_ip_jesd204_tpl_dac_framer #(
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.NUM_LANES (NUM_LANES),
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.NUM_CHANNELS (NUM_CHANNELS),
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.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
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.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
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.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
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.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
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.LINK_DATA_WIDTH (LINK_DATA_WIDTH)
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.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
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.DAC_DATA_WIDTH (DAC_DATA_WIDTH)
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) i_framer (
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.link_data (link_data),
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.dac_data (dac_data_s)
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@ -88,7 +98,8 @@ module ad_ip_jesd204_tpl_dac_core #(
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// PN generator
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ad_ip_jesd204_tpl_dac_pn #(
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH)
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION)
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) i_pn_gen (
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.clk (clk),
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.reset (dac_sync),
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@ -101,13 +112,13 @@ module ad_ip_jesd204_tpl_dac_core #(
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assign dac_valid = {NUM_CHANNELS{1'b1}};
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localparam CDW = DATA_PATH_WIDTH * 16;
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generate
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genvar i;
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for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
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ad_ip_jesd204_tpl_dac_channel #(
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
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.DATAPATH_DISABLE (DATAPATH_DISABLE),
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.DDS_TYPE (DDS_TYPE),
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.DDS_CORDIC_DW (DDS_CORDIC_DW),
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@ -115,8 +126,8 @@ module ad_ip_jesd204_tpl_dac_core #(
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) i_channel (
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.clk (clk),
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.dac_enable (enable[i]),
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.dac_data (dac_data_s[CDW*i+:CDW]),
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.dma_data (dac_ddata[CDW*i+:CDW]),
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.dac_data (dac_data_s[DAC_CDW*i+:DAC_CDW]),
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.dma_data (dac_ddata[DMA_CDW*i+:DMA_CDW]),
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.pn7_data (pn7_data),
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.pn15_data (pn15_data),
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@ -26,9 +26,12 @@
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module ad_ip_jesd204_tpl_dac_framer #(
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parameter NUM_LANES = 8,
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parameter NUM_CHANNELS = 4,
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parameter BITS_PER_SAMPLE = 16,
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parameter CONVERTER_RESOLUTION = 16,
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parameter SAMPLES_PER_FRAME = 2,
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parameter OCTETS_PER_BEAT = 4,
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parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES
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parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
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parameter DAC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
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) (
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// jesd interface
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@ -36,7 +39,7 @@ module ad_ip_jesd204_tpl_dac_framer #(
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// dac interface
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input [LINK_DATA_WIDTH-1:0] dac_data
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input [DAC_DATA_WIDTH-1:0] dac_data
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);
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/*
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@ -44,7 +47,7 @@ module ad_ip_jesd204_tpl_dac_framer #(
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* JESD204 link expects for the specified framer configuration.
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*
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* The input sample data in dac_data is expected to be grouped by converter.
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* The first sample is in the LSBs.
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* The first sample is in the LSBs. Each sample has CONVERTER_RESOLUTION bits.
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*
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* Or in other words the data in dac_data is expected to have the following
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* layout.
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@ -86,12 +89,12 @@ module ad_ip_jesd204_tpl_dac_framer #(
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* ordered in either case. That means lower bits are in the LSBs.
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*/
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localparam BITS_PER_SAMPLE = 16;
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localparam FRAMES_PER_BEAT = 8 * OCTETS_PER_BEAT / BITS_PER_LANE_PER_FRAME;
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localparam SAMPLES_PER_BEAT = LINK_DATA_WIDTH / 16;
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localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
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localparam SAMPLES_PER_BEAT = DAC_DATA_WIDTH / CONVERTER_RESOLUTION;
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localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
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localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME *
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NUM_CHANNELS / NUM_LANES;
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localparam TAIL_BITS = BITS_PER_SAMPLE - CONVERTER_RESOLUTION;
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wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
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wire [LINK_DATA_WIDTH-1:0] frame_data_s;
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@ -100,13 +103,17 @@ module ad_ip_jesd204_tpl_dac_framer #(
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generate
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genvar i;
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genvar j;
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/* Reorder samples MSB first */
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/* Reorder samples MSB first and insert tail bits */
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for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
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localparam w = BITS_PER_SAMPLE;
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localparam src_lsb = i * w;
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localparam dst_msb = LINK_DATA_WIDTH - 1 - src_lsb;
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localparam src_w = CONVERTER_RESOLUTION;
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localparam dst_w = BITS_PER_SAMPLE;
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localparam src_lsb = i * src_w;
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localparam dst_msb = LINK_DATA_WIDTH - 1 - i * dst_w;
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assign dac_data_msb[dst_msb-:w] = dac_data[src_lsb+:w];
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assign dac_data_msb[dst_msb-:src_w] = dac_data[src_lsb+:src_w];
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if (TAIL_BITS > 0) begin
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assign dac_data_msb[dst_msb-src_w-:TAIL_BITS] = {TAIL_BITS{1'b0}};
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end
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end
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/* Slice channel and pack it into frames */
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@ -81,6 +81,20 @@ ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
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GROUP $group \
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]
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ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 false [list \
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DISPLAY_NAME "Bits per Sample (N')" \
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ALLOWED_RANGES {12 16} \
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UNITS bits \
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GROUP $group \
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]
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ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
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DISPLAY_NAME "Converter Resolution (N)" \
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ALLOWED_RANGES {11 12 16} \
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UNITS bits \
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GROUP $group \
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]
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ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \
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DISPLAY_NAME "Samples per Frame (S)" \
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DISPLAY_UNITS "samples" \
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@ -141,22 +155,25 @@ proc p_ad_ip_jesd204_tpl_dac_elab {} {
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# read core parameters
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set m_num_of_lanes [get_parameter_value "NUM_LANES"]
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set m_num_of_channels [get_parameter_value "NUM_CHANNELS"]
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set channel_bus_width [expr 32*$m_num_of_lanes/$m_num_of_channels]
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set L [get_parameter_value "NUM_LANES"]
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set M [get_parameter_value "NUM_CHANNELS"]
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set NP [get_parameter_value "BITS_PER_SAMPLE"]
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# The DMA interface is always 16-bits per sample, regardless of NP
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set channel_bus_width [expr 16 * (32 * $L / ($M * $NP))]
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# link layer interface
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add_interface link_data avalon_streaming source
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add_interface_port link_data link_data data output [expr 32*$m_num_of_lanes]
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add_interface_port link_data link_data data output [expr 32 * $L]
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add_interface_port link_data link_valid valid output 1
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add_interface_port link_data link_ready ready input 1
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set_interface_property link_data associatedClock link_clk
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set_interface_property link_data dataBitsPerSymbol [expr 32*$m_num_of_lanes]
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set_interface_property link_data dataBitsPerSymbol [expr 32 * $L]
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# dma interface
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for {set i 0} {$i < $m_num_of_channels} {incr i} {
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for {set i 0} {$i < $M} {incr i} {
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add_interface dac_ch_$i conduit end
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add_interface_port dac_ch_$i dac_enable_$i enable output 1
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set_port_property dac_enable_$i fragment_list [format "enable(%d:%d)" $i $i]
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@ -86,6 +86,8 @@ foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} {
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foreach {p v} {
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"NUM_LANES" "1 2 3 4 8" \
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"NUM_CHANNELS" "1 2 4 6 8" \
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"BITS_PER_SAMPLE" "12 16" \
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"CONVERTER_RESOLUTION" "11 12 16" \
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"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
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} { \
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set_property -dict [list \
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@ -113,6 +115,8 @@ set i 0
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foreach {k v} { \
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"NUM_LANES" "Number of Lanes (L)" \
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"NUM_CHANNELS" "Number of Conveters (M)" \
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||||
"BITS_PER_SAMPLE" "Bits per Sample (N')" \
|
||||
"CONVERTER_RESOLUTION" "Converter Resolution (N)" \
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||||
"SAMPLES_PER_FRAME" "Samples per Frame (S)" \
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||||
} { \
|
||||
set p [ipgui::get_guiparamspec -name $k -component $cc]
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||||
|
|
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|||
|
|
@ -24,26 +24,33 @@
|
|||
`timescale 1ns/100ps
|
||||
|
||||
module ad_ip_jesd204_tpl_dac_pn #(
|
||||
parameter DATA_PATH_WIDTH = 4
|
||||
parameter DATA_PATH_WIDTH = 4,
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||||
parameter CONVERTER_RESOLUTION = 16
|
||||
) (
|
||||
input clk,
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||||
input reset,
|
||||
|
||||
output [DATA_PATH_WIDTH*16-1:0] pn7_data,
|
||||
output [DATA_PATH_WIDTH*16-1:0] pn15_data
|
||||
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
|
||||
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data
|
||||
);
|
||||
|
||||
localparam DW = DATA_PATH_WIDTH * 16 - 1;
|
||||
localparam CR = CONVERTER_RESOLUTION;
|
||||
localparam DW = DATA_PATH_WIDTH * CR - 1;
|
||||
|
||||
reg [DW:0] pn7_state = {DW+1{1'b1}};
|
||||
reg [DW:0] pn15_state = {DW+1{1'b1}};
|
||||
/* We need at least enough bits to store the PN state */
|
||||
localparam PN7_W = DW > 6 ? DW : 6;
|
||||
localparam PN15_W = DW > 14 ? DW : 14;
|
||||
|
||||
reg [PN7_W:0] pn7_state = {PN7_W+1{1'b1}};
|
||||
reg [PN15_W:0] pn15_state = {PN15_W+1{1'b1}};
|
||||
|
||||
wire [DW:0] pn7;
|
||||
wire [DW+7:0] pn7_full_state;
|
||||
wire [DW:0] pn7_reset;
|
||||
wire [PN7_W:0] pn7_reset;
|
||||
|
||||
wire [DW:0] pn15;
|
||||
wire [DW+15:0] pn15_full_state;
|
||||
wire [DW:0] pn15_reset;
|
||||
wire [PN15_W:0] pn15_reset;
|
||||
|
||||
/* PN7 x^7 + x^6 + 1 */
|
||||
assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1];
|
||||
|
|
@ -53,19 +60,26 @@ module ad_ip_jesd204_tpl_dac_pn #(
|
|||
assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1];
|
||||
assign pn15_full_state = {pn15_state[14:0],pn15};
|
||||
|
||||
assign pn7_reset[DW-:7] = {7{1'b1}};
|
||||
assign pn7_reset[DW-7:0] = pn7_reset[DW:7] ^ pn7_reset[DW-1:6];
|
||||
assign pn7_reset[PN7_W-:7] = {7{1'b1}};
|
||||
assign pn15_reset[PN15_W-:15] = {15{1'b1}};
|
||||
|
||||
assign pn15_reset[DW-:15] = {15{1'b1}};
|
||||
assign pn15_reset[DW-15:0] = pn15_reset[DW:15] ^ pn15_reset[DW-1:14];
|
||||
generate
|
||||
if (PN7_W >= 7) begin
|
||||
assign pn7_reset[PN7_W-7:0] = pn7_reset[PN7_W:7] ^ pn7_reset[PN7_W-1:6];
|
||||
end
|
||||
|
||||
if (PN15_W >= 15) begin
|
||||
assign pn15_reset[PN15_W-15:0] = pn15_reset[PN15_W:15] ^ pn15_reset[PN15_W-1:14];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
pn7_state <= pn7_reset;
|
||||
pn15_state <= pn15_reset;
|
||||
end else begin
|
||||
pn7_state <= pn7;
|
||||
pn15_state <= pn15;
|
||||
pn7_state <= pn7_full_state[PN7_W:0];
|
||||
pn15_state <= pn15_full_state[PN15_W:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -76,9 +90,9 @@ module ad_ip_jesd204_tpl_dac_pn #(
|
|||
* sample of the PN state and put it into the LSB sample of the output data.
|
||||
*/
|
||||
genvar i;
|
||||
for (i = 0; i <= DW; i = i + 16) begin: g_pn_swizzle
|
||||
assign pn7_data[i+:16] = pn7_state[DW-i-:16];
|
||||
assign pn15_data[i+:16] = pn15_state[DW-i-:16];
|
||||
for (i = 0; i <= DW; i = i + CR) begin: g_pn_swizzle
|
||||
assign pn7_data[i+:CR] = pn7_state[PN7_W-i-:CR];
|
||||
assign pn15_data[i+:CR] = pn15_state[PN15_W-i-:CR];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue