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util_mii_to_rmii: Initial commit

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alin724 2021-11-09 13:58:06 +02:00 committed by Alin-Tudor Sferle
parent 3da9d9fcb4
commit 170ce42e3e
6 changed files with 738 additions and 0 deletions
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2
library/Makefile
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@ -115,6 +115,7 @@ clean:
$(MAKE) -C util_gmii_to_rgmii clean
$(MAKE) -C util_i2c_mixer clean
$(MAKE) -C util_mfifo clean
$(MAKE) -C util_mii_to_rmii clean
$(MAKE) -C util_pack/util_cpack2 clean
$(MAKE) -C util_pack/util_upack2 clean
$(MAKE) -C util_pad clean
@ -240,6 +241,7 @@ lib:
$(MAKE) -C util_gmii_to_rgmii
$(MAKE) -C util_i2c_mixer
$(MAKE) -C util_mfifo
$(MAKE) -C util_mii_to_rmii
$(MAKE) -C util_pack/util_cpack2
$(MAKE) -C util_pack/util_upack2
$(MAKE) -C util_pad

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library/util_mii_to_rmii/Makefile Normal file
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####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_mii_to_rmii
GENERIC_DEPS += mac_phy_link.v
GENERIC_DEPS += phy_mac_link.v
GENERIC_DEPS += util_mii_to_rmii.v
XILINX_DEPS += util_mii_to_rmii_ip.tcl
include ../scripts/library.mk

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library/util_mii_to_rmii/mac_phy_link.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
`timescale 1ns/100ps
module mac_phy_link #(
parameter RATE_10_100 = 0
) (
input ref_clk,
input [3:0] mac_txd,
input reset_n,
input mac_tx_en,
input mac_tx_er,
output rmii_tx_en,
output [1:0] rmii_txd,
output mii_tx_clk
);
wire dibit_sample;
wire [3:0] num_w;
wire tx_dibit;
wire [4:0] reg_count_w;
reg [3:0] mac_txd_r = 4'b0;
reg mac_tx_en_r = 1'b0;
reg mac_tx_er_r = 1'b0;
reg mii_tx_clk_10_100_r = 1'b0;
reg [3:0] num_r = 4'b0;
reg [1:0] rmii_txd_r = 2'b0;
reg rmii_tx_en_r = 1'b0;
reg rising_tx_clk_r0 = 1'b0;
reg rising_tx_clk_r1 = 1'b0;
reg [4:0] reg_count = 5'b0;
reg tx_dibit_d = 1'b0;
localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1;
always @(posedge ref_clk) begin
if (!reset_n) begin
num_r <= 0;
mii_tx_clk_10_100_r <= 1'b0;
end else if (num_w == DIV_REF_CLK) begin
num_r <= 0;
mii_tx_clk_10_100_r <= ~mii_tx_clk_10_100_r;
if (!mii_tx_clk_10_100_r) begin
rising_tx_clk_r0 <= 1'b1;
rising_tx_clk_r1 <= rising_tx_clk_r0;
end else begin
rising_tx_clk_r0 <= 1'b0;
rising_tx_clk_r1 <= rising_tx_clk_r0;
end
rising_tx_clk_r1 <= rising_tx_clk_r0;
end else begin
num_r <= num_w;
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
mac_txd_r <= 4'b0;
mac_tx_en_r <= 1'b0;
mac_tx_er_r <= 1'b0;
end else begin
if (dibit_sample == 1'b1) begin
mac_txd_r <= mac_txd;
mac_tx_en_r <= mac_tx_en;
mac_tx_er_r <= mac_tx_er;
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
rmii_txd_r <= 2'b0;
rmii_tx_en_r <= 1'b0;
end else begin
if (!tx_dibit) begin
rmii_txd_r[0] <= mac_txd_r[0] ^ mac_tx_er_r;
rmii_txd_r[1] <= mac_txd_r[1] | mac_tx_er_r;
rmii_tx_en_r <= mac_tx_en_r;
end else begin
rmii_txd_r[0] <= mac_txd_r[2] ^ mac_tx_er_r;
rmii_txd_r[1] <= mac_txd_r[3] | mac_tx_er_r;
rmii_tx_en_r <= mac_tx_en_r;
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
reg_count <= 1'b0;
end else begin
if (reg_count_w == 5'b10011) begin
reg_count <= 1'b0;
end else begin
reg_count <= reg_count + 1;
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
tx_dibit_d <= 1'b0;
end else begin
tx_dibit_d <= tx_dibit;
end
end
assign dibit_sample = RATE_10_100 ? (reg_count_w == 5'b01001 ? 1'b1 : 1'b0) : rising_tx_clk_r1;
assign num_w = num_r + 1;
assign mii_tx_clk = mii_tx_clk_10_100_r;
assign reg_count_w = reg_count;
assign rmii_txd = rmii_txd_r;
assign rmii_tx_en = rmii_tx_en_r;
assign tx_dibit = ~mii_tx_clk;
endmodule

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library/util_mii_to_rmii/phy_mac_link.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
`timescale 1ns/100ps
module phy_mac_link #(
parameter RATE_10_100 = 0
) (
input ref_clk,
input reset_n,
input [1:0] phy_rxd,
input phy_crs_dv,
input phy_rx_er,
output [3:0] mii_rxd,
output mii_rx_dv,
output mii_rx_er,
output mii_crs,
output mii_col,
output mii_rx_clk
);
wire clk_phase_res;
wire data_valid_w;
wire dibit_sample;
wire eopack_w;
wire [9:0] mii_rx_dv_10mbps_w;
wire [3:0] num_w;
wire [3:0] reg_count_w;
wire sopack_w;
reg mii_rx_clk_10_100_r = 1'b0;
reg [3:0] num_r = 4'b0;
reg [3:0] reg_count = 4'b0;
reg clk_phase_r = 1'b0;
reg data_valid = 1'b0;
reg data_valid_d = 1'b0;
reg [1:0] eopack_r = 2'b0;
reg nibble_valid = 1'b0;
reg [1:0] sopack_r = 2'b0;
reg [3:0] mii_rxd_r0 = 4'b0;
reg [3:0] mii_rxd_r1 = 4'b0;
reg [3:0] mii_rxd_r2 = 4'b0;
reg mii_rx_er_r0 = 1'b0;
reg mii_rx_er_r1 = 1'b0;
reg mii_rx_er_r2 = 1'b0;
reg mii_rx_dv_r0 = 1'b0;
reg mii_rx_dv_r1 = 1'b0;
reg mii_rx_dv_r2 = 1'b0;
reg mii_rx_dv_r3 = 1'b0;
localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1;
always @(posedge ref_clk) begin
if (!reset_n) begin
num_r <= 0;
mii_rx_clk_10_100_r <= 1'b0;
end else if (num_w == DIV_REF_CLK) begin
num_r <= 0;
mii_rx_clk_10_100_r <= ~mii_rx_clk_10_100_r;
end else begin
num_r <= num_w;
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
mii_rxd_r0 <= 4'b0;
mii_rxd_r1 <= 4'b0;
mii_rxd_r2 <= 4'b0;
end else begin
if (RATE_10_100) begin
if (dibit_sample) begin
mii_rxd_r0[3:2] <= phy_rxd;
mii_rxd_r0[1:0] <= mii_rxd_r0[3:2];
if (nibble_valid | sopack_w) begin
mii_rxd_r1 <= mii_rxd_r0;
end
mii_rxd_r2 <= mii_rxd_r1;
end
end else begin
mii_rxd_r0[3:2] <= phy_rxd;
mii_rxd_r0[1:0] <= mii_rxd_r0[3:2];
if (nibble_valid | sopack_w) begin
mii_rxd_r1 <= mii_rxd_r0;
end
mii_rxd_r2 <= mii_rxd_r1;
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
mii_rx_er_r0 <= 1'b0;
mii_rx_er_r1 <= 1'b0;
mii_rx_er_r2 <= 1'b0;
end else begin
if (RATE_10_100) begin
if (dibit_sample) begin
mii_rx_er_r0 <= phy_rx_er;
mii_rx_er_r1 <= mii_rx_er_r0;
mii_rx_er_r2 <= mii_rx_er_r1;
end
end else begin
mii_rx_er_r0 <= phy_rx_er;
mii_rx_er_r1 <= mii_rx_er_r0;
mii_rx_er_r2 <= mii_rx_er_r1;
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
mii_rx_dv_r0 <= 1'b0;
mii_rx_dv_r1 <= 1'b0;
mii_rx_dv_r2 <= 1'b0;
mii_rx_dv_r3 <= 1'b0;
end else begin
if (RATE_10_100) begin
if (dibit_sample) begin
mii_rx_dv_r0 <= phy_crs_dv;
mii_rx_dv_r1 <= mii_rx_dv_r0;
mii_rx_dv_r2 <= mii_rx_dv_r1;
mii_rx_dv_r3 <= mii_rx_dv_r2;
end
end else begin
mii_rx_dv_r0 <= phy_crs_dv;
mii_rx_dv_r1 <= mii_rx_dv_r0;
mii_rx_dv_r2 <= mii_rx_dv_r1;
mii_rx_dv_r3 <= mii_rx_dv_r2;
end
end
end
always @(posedge ref_clk) begin
if (!reset_n || eopack_w) begin
sopack_r[1:0] <= 2'b0;
end else begin
if (RATE_10_100) begin
if (dibit_sample) begin
sopack_r[1] <= sopack_r[0];
end
if (dibit_sample && (mii_rxd_r0[3:2] == 2'b01) && (mii_rx_dv_r0 == 1'b1) && (sopack_w == 1'b0)) begin
sopack_r[0] <= 1'b1;
end
end else begin
sopack_r[1] <= sopack_r[0];
if ((mii_rxd_r0[3:2] == 2'b01) && (mii_rx_dv_r0 == 1'b1) && (sopack_w == 1'b0)) begin
sopack_r[0] <= 1'b1;
end
end
end
end
always @(posedge ref_clk) begin
if (!reset_n || sopack_w) begin
eopack_r[1:0] <= 2'b0;
end else begin
if (RATE_10_100) begin
if (dibit_sample) begin
eopack_r[1] <= eopack_r[0];
end
if (dibit_sample && (mii_rx_dv_r0 == 1'b0) && (mii_rx_dv_r1 == 1'b0) && (eopack_w == 1'b0)) begin
eopack_r[0] <= 1'b1;
end
end else begin
eopack_r[1] <= eopack_r[0];
if ((mii_rx_dv_r0 == 1'b0) && (mii_rx_dv_r1 == 1'b0) && (eopack_w == 1'b0)) begin
eopack_r[0] <= 1'b1;
end
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
data_valid <= 1'b0;
end else begin
if (RATE_10_100) begin
if (dibit_sample && sopack_w) begin
data_valid <= 1'b1;
end else if (dibit_sample && eopack_w) begin
data_valid <= 1'b0;
end
end else begin
if (sopack_w) begin
data_valid <= 1'b1;
end else if (eopack_w) begin
data_valid <= 1'b0;
end
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
data_valid_d <= 1'b0;
end else begin
data_valid_d <= data_valid;
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
clk_phase_r <= 1'b0;
nibble_valid <= 1'b0;
end else begin
if (sopack_w) begin
clk_phase_r <= mii_rx_clk;
nibble_valid <= 1'b0;
end else begin
if (dibit_sample) begin
nibble_valid <= ~nibble_valid;
end
end
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
reg_count <= 1'b0;
end else begin
if (reg_count_w == 4'b1001) begin
reg_count <= 1'b0;
end else begin
reg_count <= reg_count + 1;
end
end
end
assign clk_phase_res = clk_phase_r;
assign data_valid_w = RATE_10_100 ? data_valid : (clk_phase_res ? data_valid : data_valid_d);
assign dibit_sample = (reg_count_w == 4'b0101) ? 1'b1 : 1'b0;
assign eopack_w = eopack_r[0] & (!eopack_r[1]);
assign mii_crs = mii_rx_dv_r0;
assign mii_rxd = RATE_10_100 ? (mii_rx_dv ? mii_rxd_r1 : 4'b0) : (mii_rx_dv ? (clk_phase_res ? mii_rxd_r1 : mii_rxd_r2) : 4'b0);
assign mii_rx_clk = mii_rx_clk_10_100_r;
assign mii_rx_dv = data_valid_w ? 1'b1 : 1'b0;
assign mii_rx_er = mii_rx_er_r2;
assign num_w = num_r + 1;
assign reg_count_w = reg_count;
assign sopack_w = sopack_r[0] & (!sopack_r[1]);
endmodule

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library/util_mii_to_rmii/util_mii_to_rmii.v Normal file
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@ -0,0 +1,189 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_mii_to_rmii #(
parameter INTF_CFG = 0,
parameter RATE_10_100 = 0
) (
// MAC to MII(PHY)
input mac_tx_en,
input [3:0] mac_txd,
input mac_tx_er,
//MII to MAC
output mii_tx_clk,
output mii_rx_clk,
output mii_col,
output mii_crs,
output mii_rx_dv,
output mii_rx_er,
output [3:0] mii_rxd,
// RMII to PHY
output [1:0] rmii_txd,
output rmii_tx_en,
// PHY to RMII
input [1:0] phy_rxd,
input phy_crs_dv,
input phy_rx_er,
// External
input ref_clk,
input reset_n
);
reg mac_tx_en_r1 = 1'b0;
reg [3:0] mac_txd_r1 = 4'b0;
reg mac_tx_er_r1 = 1'b0;
reg phy_crs_dv_r1 = 1'b0;
reg [1:0] phy_rxd_r1 = 2'b0;
reg phy_rx_er_r1 = 1'b0;
reg mii_tx_clk_r1 = 1'b0;
reg mii_rx_clk_r1 = 1'b0;
reg mii_col_r1 = 1'b0;
reg mii_crs_r1 = 1'b0;
reg mii_rx_dv_r1 = 1'b0;
reg mii_rx_er_r1 = 1'b0;
reg [3:0] mii_rxd_r1 = 4'b0;
reg [1:0] rmii_txd_r1 = 2'b0;
reg rmii_tx_en_r1 = 1'b0;
reg mac_tx_en_r2 = 1'b0;
reg [3:0] mac_txd_r2 = 4'b0;
reg mac_tx_er_r2 = 1'b0;
reg phy_crs_dv_r2 = 1'b0;
reg [1:0] phy_rxd_r2 = 2'b0;
reg phy_rx_er_r2 = 1'b0;
wire mii_tx_clk_r2;
wire mii_rx_clk_r2;
wire mii_col_r2;
wire mii_crs_r2;
wire mii_rx_dv_r2;
wire mii_rx_er_r2;
wire [3:0] mii_rxd_r2;
wire [1:0] rmii_txd_r2;
wire rmii_tx_en_r2;
//inputs
always @(posedge ref_clk) begin
if (!reset_n) begin
mac_tx_en_r1 <= 1'b0;
mac_tx_en_r2 <= 1'b0;
mac_txd_r1 <= 4'b0;
mac_txd_r2 <= 4'b0;
mac_tx_er_r1 <= 1'b0;
mac_tx_er_r2 <= 1'b0;
phy_crs_dv_r1 <= 1'b0;
phy_crs_dv_r2 <= 1'b0;
phy_rxd_r1 <= 2'b0;
phy_rx_er_r1 <= 1'b0;
phy_rxd_r2 <= 2'b0;
end else begin
mac_tx_en_r1 <= mac_tx_en;
mac_tx_en_r2 <= mac_tx_en_r1;
mac_txd_r1 <= mac_txd;
mac_txd_r2 <= mac_txd_r1;
mac_tx_er_r1 <= mac_tx_er;
mac_tx_er_r2 <= mac_tx_er_r1;
phy_crs_dv_r1 <= phy_crs_dv;
phy_crs_dv_r2 <= phy_crs_dv_r1;
phy_rxd_r1 <= phy_rxd;
phy_rxd_r2 <= phy_rxd_r1;
phy_rx_er_r1 <= phy_rx_er;
phy_rx_er_r2 <= phy_rx_er_r1;
end
end
//outputs
always @(posedge ref_clk) begin
if (!reset_n) begin
mii_col_r1 <= 1'b0;
mii_crs_r1 <= 1'b0;
mii_rx_dv_r1 <= 1'b0;
mii_rx_er_r1 <= 1'b0;
mii_rxd_r1 <= 4'b0;
rmii_txd_r1 <= 2'b0;
rmii_tx_en_r1 <= 1'b0;
mii_tx_clk_r1 <= 1'b0;
mii_rx_clk_r1 <= 1'b0;
end else begin
mii_tx_clk_r1 <= mii_tx_clk_r2;
mii_rx_clk_r1 <= mii_rx_clk_r2;
mii_col_r1 <= mii_crs_r2 & mac_tx_en_r2;
mii_crs_r1 <= mii_crs_r2;
mii_rx_dv_r1 <= mii_rx_dv_r2;
mii_rx_er_r1 <= mii_rx_er_r2;
mii_rxd_r1 <= mii_rxd_r2;
rmii_txd_r1 <= rmii_txd_r2;
rmii_tx_en_r1 <= rmii_tx_en_r2;
end
end
assign mii_crs = mii_crs_r1;
assign mii_col = mii_col_r1;
assign mii_rx_dv = mii_rx_dv_r1;
assign mii_rx_er = mii_rx_er_r1;
assign mii_rxd = mii_rxd_r1;
assign rmii_txd = rmii_txd_r1;
assign rmii_tx_en = rmii_tx_en_r1;
assign mii_rx_clk = mii_rx_clk_r1;
assign mii_tx_clk = mii_tx_clk_r1;
mac_phy_link #(
.RATE_10_100(RATE_10_100)
) mac_phy_link_inst (
.ref_clk(ref_clk),
.reset_n(reset_n),
.mac_tx_en(mac_tx_en_r2),
.mac_txd(mac_txd_r2),
.mac_tx_er(mac_tx_er_r2),
.mii_tx_clk(mii_tx_clk_r2),
.rmii_txd(rmii_txd_r2),
.rmii_tx_en(rmii_tx_en_r2));
phy_mac_link #(
.RATE_10_100(RATE_10_100)
) phy_mac_link_inst (
.ref_clk(ref_clk),
.reset_n(reset_n),
.mii_crs(mii_crs_r2),
.mii_rx_dv(mii_rx_dv_r2),
.mii_rx_er(mii_rx_er_r2),
.mii_rxd(mii_rxd_r2),
.mii_rx_clk(mii_rx_clk_r2),
.phy_rxd(phy_rxd_r2),
.phy_crs_dv(phy_crs_dv_r2),
.phy_rx_er(phy_rx_er_r2));
endmodule

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library/util_mii_to_rmii/util_mii_to_rmii_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_mii_to_rmii
adi_ip_files util_mii_to_rmii [list \
"mac_phy_link.v" \
"phy_mac_link.v" \
"util_mii_to_rmii.v" ]
adi_ip_properties_lite util_mii_to_rmii
adi_add_bus "GMII" "slave" \
"xilinx.com:interface:gmii_rtl:1.0" \
"xilinx.com:interface:gmii:1.0" \
{
{"mii_col" "COL"} \
{"mii_crs" "CRS"} \
{"mii_rxd" "RXD"} \
{"mii_rx_clk" "RX_CLK"} \
{"mii_rx_dv" "RX_DV"} \
{"mii_rx_er" "RX_ER"} \
{"mac_txd" "TXD"} \
{"mii_tx_clk" "TX_CLK"} \
{"mac_tx_en" "TX_EN"} \
{"mac_tx_er" "TX_ER"} \
}
adi_add_bus "MII" "slave" \
"xilinx.com:interface:mii_rtl:1.0" \
"xilinx.com:interface:mii:1.0" \
{
{"mii_col" "COL"} \
{"mii_crs" "CRS"} \
{"mii_rxd" "RXD"} \
{"mii_rx_clk" "RX_CLK"} \
{"mii_rx_dv" "RX_DV"} \
{"mii_rx_er" "RX_ER"} \
{"mac_txd" "TXD"} \
{"mii_tx_clk" "TX_CLK"} \
{"mac_tx_en" "TX_EN"} \
{"mac_tx_er" "TX_ER"} \
}
adi_add_bus "RMII" "master" \
"xilinx.com:interface:rmii_rtl:1.0" \
"xilinx.com:interface:rmii:1.0" \
{
{"phy_crs_dv" "CRS_DV"} \
{"phy_rxd" "RXD"} \
{"phy_rx_er" "RX_ER"} \
{"rmii_txd" "TXD"} \
{"rmii_tx_en" "TX_EN"} \
}
adi_set_bus_dependency "MII" "MII" \
"(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 0)"
adi_set_bus_dependency "GMII" "GMII" \
"(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 1)"
set cc [ipx::current_core]
ipx::infer_bus_interface reset_n xilinx.com:signal:reset_rtl:1.0 $cc
ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 $cc
## Customize XGUI layout
set_property display_name "util_mii_to_rmii" $cc
set_property description "MII to RMII Converter IP" $cc
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" { \
"MII" "0" \
"GMII" "1" \
} \
] \
[ipx::get_user_parameters INTF_CFG -of_objects $cc]
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" { \
"100Mbps" "0" \
"10Mbps" "1" \
} \
] \
[ipx::get_user_parameters RATE_10_100 -of_objects $cc]
ipgui::add_param -name "INTF_CFG" -component $cc
set p [ipgui::get_guiparamspec -name "INTF_CFG" -component $cc]
set_property -dict [list \
"widget" "comboBox" \
"display_name" "Interface Selection" \
] $p
ipgui::add_param -name "RATE_10_100" -component $cc
set p [ipgui::get_guiparamspec -name "RATE_10_100" -component $cc]
set_property -dict [list \
"widget" "comboBox" \
"display_name" "Rate Selection" \
] $p
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core $cc