ad_serdes: Add features and update their instances in /library

- ad_serdes_in:
  * Removed unused ports: loaden, phase, locked
  * Added IODELAY_ENABLE is set to be by default 1
  * Added conditional instantiation (using IODELAY_ENABLE) to IDELAY modules
  * Added conditional instantiation (using IODELAY_CTRL_ENABLED) to IDELAYCTRL module, based on IODELAY_ENABLE

- library: Update ad_serdes_in instances: add IODELAY_ENABLE
   * Edited in:
     * axi_ad9434
     * axi_ad9684
     * axi_adrv9001

- ad_serdes_out:
  * Removed unused port: loaden

- library: Update ad_serdes_out instances
   * Edited in:
     * axi_ad9122
     * axi_ad9739a
     * axi_ad9783
     * axi_adrv9001

- ad_serdes_clk:
  * Remove unused ports: loaden, phase

- library: Update ad_serdes_clk instances
   * Edited in:
     * axi_ad9122
     * axi_ad9434
     * axi_ad9684

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

library/axi_ad9122/axi_ad9122_if.v

@@ -112,7 +112,6 @@ module axi_ad9122_if #(
   // internal signals
 
   wire            dac_out_clk;
-  wire            loaden_s;
 
   // dac status
 
@@ -136,7 +135,6 @@ module axi_ad9122_if #(
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (loaden_s),
     .data_oe (1'b1),
     .data_s0 (dac_data_i0),
     .data_s1 (dac_data_q0),
@@ -160,7 +158,6 @@ module axi_ad9122_if #(
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (loaden_s),
     .data_oe (1'b1),
     .data_s0 (dac_frame_i0),
     .data_s1 (dac_frame_q0),
@@ -184,7 +181,6 @@ module axi_ad9122_if #(
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (loaden_s),
     .data_oe (1'b1),
     .data_s0 (1'b1),
     .data_s1 (1'b0),
@@ -216,8 +212,6 @@ module axi_ad9122_if #(
     .clk (dac_clk),
     .div_clk (dac_div_clk),
     .out_clk (dac_out_clk),
-    .loaden (loaden_s),
-    .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

library/axi_ad9434/axi_ad9434.v

@@ -43,6 +43,7 @@ module axi_ad9434 #(
   parameter FPGA_FAMILY = 0,
   parameter SPEED_GRADE = 0,
   parameter DEV_PACKAGE = 0,
+  parameter IODELAY_ENABLE = 1,
   parameter IO_DELAY_GROUP = "dev_if_delay_group"
 ) (
 
@@ -133,6 +134,7 @@ module axi_ad9434 #(
 
   axi_ad9434_if #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IO_DELAY_GROUP(IO_DELAY_GROUP)
   ) i_if (
     .adc_clk_in_p(adc_clk_in_p),

library/axi_ad9434/axi_ad9434_if.v

@@ -38,6 +38,7 @@
 module axi_ad9434_if #(
 
   parameter FPGA_TECHNOLOGY = 0,
+  parameter IODELAY_ENABLE = 1,
   parameter IO_DELAY_GROUP = "dev_if_delay_group"
 ) (
 
@@ -102,6 +103,7 @@ module axi_ad9434_if #(
   // data interface
   ad_serdes_in #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IODELAY_CTRL(0),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
@@ -111,9 +113,6 @@ module axi_ad9434_if #(
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
-    .loaden(1'b0),
-    .phase(8'b0),
-    .locked(1'b0),
     .data_s0(adc_data[47:36]),
     .data_s1(adc_data[35:24]),
     .data_s2(adc_data[23:12]),
@@ -135,6 +134,7 @@ module axi_ad9434_if #(
   // over-range interface
   ad_serdes_in #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IODELAY_CTRL(1),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
@@ -144,9 +144,6 @@ module axi_ad9434_if #(
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
-    .loaden(1'b0),
-    .phase(8'b0),
-    .locked(1'b0),
     .data_s0(adc_or_s[3]),
     .data_s1(adc_or_s[2]),
     .data_s2(adc_or_s[1]),
@@ -183,8 +180,6 @@ module axi_ad9434_if #(
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
     .out_clk (),
-    .loaden (),
-    .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

library/axi_ad9684/axi_ad9684.v

@@ -42,6 +42,7 @@ module axi_ad9684 #(
   parameter FPGA_FAMILY = 0,
   parameter SPEED_GRADE = 0,
   parameter DEV_PACKAGE = 0,
+  parameter IODELAY_ENABLE = 1,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
   parameter OR_STATUS = 1
 ) (
@@ -168,6 +169,7 @@ module axi_ad9684 #(
 
   axi_ad9684_if #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IO_DELAY_GROUP(IO_DELAY_GROUP),
     .OR_STATUS (OR_STATUS)
   ) i_ad9684_if (

library/axi_ad9684/axi_ad9684_if.v

@@ -38,6 +38,7 @@
 module axi_ad9684_if #(
 
   parameter FPGA_TECHNOLOGY = 0,
+  parameter IODELAY_ENABLE = 1,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
   parameter OR_STATUS = 0
 ) (
@@ -94,7 +95,6 @@ module axi_ad9684_if #(
   wire            adc_div_clk;
   wire  [ 1:0]    adc_data_or_a_s;
   wire  [ 1:0]    adc_data_or_b_s;
-  wire            loaden_s;
   wire  [ 7:0]    phase_s;
 
   genvar          l_inst;
@@ -108,6 +108,7 @@ module axi_ad9684_if #(
 
   ad_serdes_in #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IODELAY_CTRL(1),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(DDR_OR_SDR_N),
@@ -116,9 +117,6 @@ module axi_ad9684_if #(
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
-    .loaden(loaden_s),
-    .phase(phase_s),
-    .locked(1'b0),
     .data_s0(adc_data_b[27:14]),
     .data_s1(adc_data_a[27:14]),
     .data_s2(adc_data_b[13: 0]),
@@ -141,6 +139,7 @@ module axi_ad9684_if #(
 
     ad_serdes_in #(
       .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
+      .IODELAY_ENABLE (IODELAY_ENABLE),
       .IODELAY_CTRL(0),
       .IODELAY_GROUP(IO_DELAY_GROUP),
       .DDR_OR_SDR_N(DDR_OR_SDR_N),
@@ -149,9 +148,6 @@ module axi_ad9684_if #(
       .rst(adc_rst),
       .clk(adc_clk_in),
       .div_clk(adc_div_clk),
-      .loaden(loaden_s),
-      .phase(phase_s),
-      .locked(1'b0),
       .data_s0(adc_data_or_b_s[1]),
       .data_s1(adc_data_or_a_s[1]),
       .data_s2(adc_data_or_b_s[0]),
@@ -197,8 +193,6 @@ module axi_ad9684_if #(
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
     .out_clk (),
-    .loaden (loaden_s),
-    .phase (phase_s),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

library/axi_ad9739a/axi_ad9739a_if.v

@@ -108,7 +108,6 @@ module axi_ad9739a_if #(
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
     .data_oe (1'b1),
     .data_s0 (dac_data_00[15:2]),
     .data_s1 (dac_data_02[15:2]),
@@ -133,7 +132,6 @@ module axi_ad9739a_if #(
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
     .data_oe (1'b1),
     .data_s0 (dac_data_01[15:2]),
     .data_s1 (dac_data_03[15:2]),
@@ -158,7 +156,6 @@ module axi_ad9739a_if #(
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
     .data_oe (1'b1),
     .data_s0 (1'b1),
     .data_s1 (1'b0),

library/axi_ad9783/axi_ad9783_if.v

@@ -98,7 +98,6 @@ module axi_ad9783_if #(
     .rst (dac_rst),
     .clk (dac_clk_s),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
     .data_oe (1'b1),
     .data_s0 (dac_data_a0),
     .data_s1 (dac_data_b0),
@@ -123,7 +122,6 @@ module axi_ad9783_if #(
     .rst (dac_rst),
     .clk (dac_clk_s),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
     .data_oe (1'b1),
     .data_s0 (1'b1),
     .data_s1 (1'b0),

library/axi_adrv9001/adrv9001_rx.v

@@ -40,6 +40,7 @@ module adrv9001_rx #(
   parameter FPGA_TECHNOLOGY = 0,
   parameter NUM_LANES = 3,
   parameter DRP_WIDTH = 5,
+  parameter IODELAY_ENABLE = 1,
   parameter IODELAY_CTRL = 0,
   parameter USE_BUFG = 0,
   parameter IO_DELAY_GROUP = "dev_if_delay_group"
@@ -111,6 +112,7 @@ module adrv9001_rx #(
     .CMOS_LVDS_N (CMOS_LVDS_N),
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (IODELAY_CTRL),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IODELAY_GROUP (IO_DELAY_GROUP),
     .DDR_OR_SDR_N (DDR_OR_SDR_N),
     .DATA_WIDTH (NUM_LANES),
@@ -120,9 +122,6 @@ module adrv9001_rx #(
     .rst (adc_rst|ssi_rst),
     .clk (adc_clk_in_fast),
     .div_clk (adc_clk_div),
-    .loaden (1'b0),
-    .phase (8'b0),
-    .locked (1'b0),
     .data_s0 (data_s0),
     .data_s1 (data_s1),
     .data_s2 (data_s2),

library/axi_adrv9001/adrv9001_tx.v

@@ -108,7 +108,6 @@ module adrv9001_tx #(
     .rst (dac_rst|ssi_rst),
     .clk (dac_fast_clk),
     .div_clk (dac_clk_div),
-    .loaden (1'b0),
     .data_oe (tx_output_enable),
     .data_s0 (data_s0),
     .data_s1 (data_s1),

library/axi_adrv9001/axi_adrv9001.v

@@ -47,6 +47,7 @@ module axi_adrv9001 #(
   parameter RX_USE_BUFG = 0,
   parameter TX_USE_BUFG = 0,
   parameter IODELAY_CTRL = 1,
+  parameter IODELAY_ENABLE = 1,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
   parameter FPGA_TECHNOLOGY = 0,
   parameter FPGA_FAMILY = 0,
@@ -282,6 +283,7 @@ module axi_adrv9001 #(
     .RX_USE_BUFG (RX_USE_BUFG),
     .TX_USE_BUFG (TX_USE_BUFG),
     .IODELAY_CTRL (IODELAY_CTRL),
+    .IODELAY_ENABLE (IODELAY_ENABLE),
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
     .DISABLE_RX2_SSI (DISABLE_RX2_SSI),
     .DISABLE_TX2_SSI (DISABLE_TX2_SSI),

library/axi_adrv9001/axi_adrv9001_if.v

@@ -45,6 +45,7 @@ module axi_adrv9001_if #(
   parameter DISABLE_RX2_SSI = 0,
   parameter DISABLE_TX2_SSI = 0,
   parameter IODELAY_CTRL = 1,
+  parameter IODELAY_ENABLE = 1,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
   parameter USE_RX_CLK_FOR_TX = 0
 ) (
@@ -210,6 +211,7 @@ module axi_adrv9001_if #(
       .NUM_LANES (NUM_LANES),
       .DRP_WIDTH (DRP_WIDTH),
       .IODELAY_CTRL (IODELAY_CTRL),
+      .IODELAY_ENABLE (IODELAY_ENABLE),
       .USE_BUFG (RX_USE_BUFG),
       .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"})
     ) i_rx_1_phy (
@@ -276,6 +278,7 @@ module axi_adrv9001_if #(
         .NUM_LANES (NUM_LANES),
         .DRP_WIDTH (DRP_WIDTH),
         .IODELAY_CTRL (0),
+        .IODELAY_ENABLE (IODELAY_ENABLE),
         .USE_BUFG (RX_USE_BUFG),
         .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"})
       ) i_rx_2_phy (

library/xilinx/common/ad_serdes_clk.v

@@ -58,8 +58,6 @@ module ad_serdes_clk #(
   output          clk,
   output          div_clk,
   output          out_clk,
-  output          loaden,
-  output  [ 7:0]  phase,
 
   // drp interface
 
@@ -82,8 +80,6 @@ module ad_serdes_clk #(
 
   // defaults
 
-  assign loaden = 'd0;
-  assign phase = 'd0;
   assign up_drp_rdata[31:16] = 'd0;
 
   // instantiations

library/xilinx/common/ad_serdes_in.v

@@ -42,6 +42,7 @@ module ad_serdes_in #(
   parameter   SERDES_FACTOR = 8,
   parameter   DATA_WIDTH = 16,
   parameter   DRP_WIDTH = 5,
+  parameter   IODELAY_ENABLE = 1,
   parameter   IODELAY_CTRL = 0,
   parameter   IODELAY_GROUP = "dev_if_delay_group",
   parameter   REFCLK_FREQUENCY = 200
@@ -52,9 +53,6 @@ module ad_serdes_in #(
   input                           rst,
   input                           clk,
   input                           div_clk,
-  input                           loaden,
-  input   [ 7:0]                  phase,
-  input                           locked,
 
   // data interface
 
@@ -88,11 +86,13 @@ module ad_serdes_in #(
   localparam  ULTRASCALE_PLUS  = 3;
   localparam  DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR";
 
+  localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
   localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
                           FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
                           FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" :
                           "UNSUPPORTED";
-
+  // when ULTRASCALE_PLUS, use ULTRASCALE because IDELAYCTRL is the same for both
+  // and doesn't know ULTRASCALE_PLUS string
   localparam SIM_DEVICE_IDELAYCTRL = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
                           FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
                           FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE" :
@@ -108,7 +108,7 @@ module ad_serdes_in #(
   // delay controller
 
   generate
-  if (IODELAY_CTRL == 1) begin
+  if (IODELAY_CTRL_ENABLED == 1) begin
     (* IODELAY_GROUP = IODELAY_GROUP *)
     IDELAYCTRL #(
       .SIM_DEVICE(SIM_DEVICE_IDELAYCTRL)
@@ -122,6 +122,9 @@ module ad_serdes_in #(
   endgenerate
 
   // received data interface: ibuf -> idelay -> iserdes
+
+  // ibuf
+
   genvar l_inst;
   generate
     for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io
@@ -138,6 +141,14 @@ module ad_serdes_in #(
     end
   endgenerate
 
+  // bypass IDELAY
+
+  generate
+  if (IODELAY_ENABLE == 0) begin
+    assign data_in_idelay_s = data_in_ibuf_s;
+  end
+  endgenerate
+
   reg [6:0] serdes_rst_seq;
   wire      serdes_rst     = serdes_rst_seq [6];
 
@@ -147,9 +158,12 @@ module ad_serdes_in #(
       else       serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
   end
 
+  // idelay + iserdes
+
   generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
     for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
+      if (IODELAY_ENABLE == 1) begin
       (* IODELAY_GROUP = IODELAY_GROUP *)
       IDELAYE2 #(
         .CINVCTRL_SEL ("FALSE"),
@@ -173,6 +187,7 @@ module ad_serdes_in #(
         .LD (up_dld[l_inst]),
         .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]),
         .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]));
+      end
 
       ISERDESE2  #(
         .DATA_RATE (DATA_RATE),
@@ -231,6 +246,8 @@ module ad_serdes_in #(
     for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
     wire   div_dld;
+    wire   en_vtc;
+    wire   ld_cnt;
     reg [4:0] vtc_cnt = {5{1'b1}};
 
     sync_event sync_load (
@@ -239,6 +256,7 @@ module ad_serdes_in #(
       .out_clk (div_clk),
       .out_event (div_dld));
 
+    if (IODELAY_ENABLE == 1) begin
     (* IODELAY_GROUP = IODELAY_GROUP *)
     IDELAYE3 #(
       .CASCADE ("NONE"),          // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
@@ -267,6 +285,7 @@ module ad_serdes_in #(
       .INC (1'b0),                                        // 1-bit input: Increment / Decrement tap delay input
       .LOAD (ld_cnt),                                     // 1-bit input: Load DELAY_VALUE input
       .RST (rst));                                        // 1-bit input: Asynchronous Reset to the DELAY_VALUE
+    end
 
     always @(posedge div_clk) begin
       if (div_dld) begin

library/xilinx/common/ad_serdes_out.v

@@ -50,7 +50,6 @@ module ad_serdes_out #(
   input                       rst,
   input                       clk,
   input                       div_clk,
-  input                       loaden,
 
   // data interface
   input                       data_oe,
@@ -99,10 +98,14 @@ module ad_serdes_out #(
       else       serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
   end
 
+  // transmit data path: oserdes -> obuf
+
   genvar l_inst;
   generate
   for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
+    // oserdes
+
     if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
       OSERDESE2  #(
         .DATA_RATE_OQ (DR_OQ_DDR),
@@ -161,9 +164,10 @@ module ad_serdes_out #(
         .RST (serdes_rst));
     end
 
-    if (CMOS_LVDS_N == 0) begin
+    // obuf
 
-      OBUFTDS i_obuf (
+    if (CMOS_LVDS_N == 0) begin
+      OBUFTDS i_obuftds (
         .T (data_t[l_inst]),
         .I (data_out_s[l_inst]),
         .O (data_out_p[l_inst]),