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ad9361: add ddr-edgesel

main
Rejeesh Kutty 2015-05-06 16:58:08 -04:00
parent a8534a9c02
commit 176a4a4b76
1 changed files with 3 additions and 1 deletions
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4
library/axi_ad9361/axi_ad9361_rx.v
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@ -50,6 +50,7 @@ module axi_ad9361_rx (
adc_data, adc_data,
adc_status, adc_status,
adc_r1_mode, adc_r1_mode,
adc_ddr_edgesel,
dac_data, dac_data,
// delay interface // delay interface
@ -112,6 +113,7 @@ module axi_ad9361_rx (
input [47:0] adc_data; input [47:0] adc_data;
input adc_status; input adc_status;
output adc_r1_mode; output adc_r1_mode;
output adc_ddr_edgesel;
input [47:0] dac_data; input [47:0] dac_data;
// delay interface // delay interface
@ -342,7 +344,7 @@ module axi_ad9361_rx (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_r1_mode (adc_r1_mode), .adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (), .adc_ddr_edgesel (adc_ddr_edgesel),
.adc_pin_mode (), .adc_pin_mode (),
.adc_status (adc_status), .adc_status (adc_status),
.adc_sync_status(), .adc_sync_status(),