avl_dacfifo: Fix the loopback of avl_xfer_req
When the read FSM is not in a burst, the incomming avl_xfer_req can be looped back to the write module.main
parent
610a237730
commit
17c749962c
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@ -182,7 +182,9 @@ module avl_dacfifo_rd #(
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if (avl_reset == 1'b1) begin
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if (avl_reset == 1'b1) begin
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avl_xfer_req_out <= 1'b0;
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avl_xfer_req_out <= 1'b0;
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end else begin
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end else begin
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if ((avl_read_state == IDLE) || (avl_read_state == XFER_STAGING)) begin
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if ((avl_read_state == IDLE) ||
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(avl_read_state == XFER_STAGING) ||
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(avl_read_state == XFER_END)) begin
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avl_xfer_req_out <= avl_xfer_req_in;
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avl_xfer_req_out <= avl_xfer_req_in;
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end
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end
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end
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end
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@ -203,12 +205,16 @@ module avl_dacfifo_rd #(
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end
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end
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end
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end
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XFER_STAGING : begin
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XFER_STAGING : begin
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if (avl_mem_request_data == 1'b1) begin
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if (avl_xfer_req_in == 1'b1) begin
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if (avl_address + AVL_ARINCR <= avl_last_address) begin
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if (avl_mem_request_data == 1'b1) begin
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avl_read_state <= XFER_FULL_BURST;
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if (avl_address + AVL_ARINCR <= avl_last_address) begin
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end else begin
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avl_read_state <= XFER_FULL_BURST;
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avl_read_state <= XFER_PARTIAL_BURST;
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end else begin
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avl_read_state <= XFER_PARTIAL_BURST;
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end
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end
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end
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end else begin
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avl_read_state <= IDLE;
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end
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end
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end
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end
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// Avalon transaction with full burst length
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// Avalon transaction with full burst length
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