From 180a80493bd04b672669208106a6b5cf952552d7 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 21 Apr 2017 13:26:37 +0300 Subject: [PATCH] avl_dacfifo: Initial commit --- library/altera/avl_dacfifo/avl_dacfifo.sdc | 12 + library/altera/avl_dacfifo/avl_dacfifo.v | 257 +++++++++ .../altera/avl_dacfifo/avl_dacfifo_constr.sdc | 12 + library/altera/avl_dacfifo/avl_dacfifo_hw.tcl | 63 +++ library/altera/avl_dacfifo/avl_dacfifo_rd.v | 359 ++++++++++++ library/altera/avl_dacfifo/avl_dacfifo_wr.v | 509 ++++++++++++++++++ 6 files changed, 1212 insertions(+) create mode 100644 library/altera/avl_dacfifo/avl_dacfifo.sdc create mode 100644 library/altera/avl_dacfifo/avl_dacfifo.v create mode 100644 library/altera/avl_dacfifo/avl_dacfifo_constr.sdc create mode 100644 library/altera/avl_dacfifo/avl_dacfifo_hw.tcl create mode 100644 library/altera/avl_dacfifo/avl_dacfifo_rd.v create mode 100644 library/altera/avl_dacfifo/avl_dacfifo_wr.v diff --git a/library/altera/avl_dacfifo/avl_dacfifo.sdc b/library/altera/avl_dacfifo/avl_dacfifo.sdc new file mode 100644 index 000000000..10b929caf --- /dev/null +++ b/library/altera/avl_dacfifo/avl_dacfifo.sdc @@ -0,0 +1,12 @@ +# CDC paths + +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|dac_mem_rd_address_g*] -to [get_registers *avl_dacfifo_rd:i_rd|avl_mem_rd_address_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_wr_address_g*] -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_wr_address_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_xfer_req*] -to [get_registers *avl_dacfifo_rd:i_rd|dac_avl_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_mem_raddr_g*] -to [get_registers *avl_dacfifo_wr:i_wr|dma_mem_raddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_write_xfer_req*] -to [get_registers *avl_dacfifo_wr:i_wr|dma_avl_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_read_control*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_mem_fetch_waddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_last_beat_ack*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_last_beat_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_last_beats*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_last_beats_m1*] + diff --git a/library/altera/avl_dacfifo/avl_dacfifo.v b/library/altera/avl_dacfifo/avl_dacfifo.v new file mode 100644 index 000000000..f1e071bf3 --- /dev/null +++ b/library/altera/avl_dacfifo/avl_dacfifo.v @@ -0,0 +1,257 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_dacfifo #( + + parameter DAC_DATA_WIDTH = 64, + parameter DMA_DATA_WIDTH = 64, + parameter AVL_DATA_WIDTH = 512, + parameter AVL_BASE_ADDRESS = 32'h00000000, + parameter AVL_ADDRESS_LIMIT = 32'h1fffffff) ( + + // dma interface + + input dma_clk, + input dma_rst, + input dma_valid, + input [(DMA_DATA_WIDTH-1):0] dma_data, + output reg dma_ready, + input dma_xfer_req, + input dma_xfer_last, + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf, + output reg dac_xfer_out, + + input bypass, + + // avalon interface + + input avl_clk, + input avl_reset, + + output reg [ 24:0] avl_address, + output reg [ 6:0] avl_burstcount, + output reg [ 63:0] avl_byteenable, + output reg avl_read, + input [511:0] avl_readdata, + input avl_readdata_valid, + input avl_ready, + output reg avl_write, + output reg [511:0] avl_writedata); + + localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0; + + // internal register + + reg dma_bypass_m1 = 1'b0; + reg dma_bypass = 1'b0; + reg dac_bypass_m1 = 1'b0; + reg dac_bypass = 1'b0; + reg dac_xfer_out_m1 = 1'b0; + reg dac_xfer_out_bypass = 1'b0; + + // internal signals + + wire dma_ready_wr_s; + wire avl_read_s; + wire avl_write_s; + wire avl_writedata_s; + wire [ 24:0] avl_wr_address_s; + wire [ 24:0] avl_rd_address_s; + wire [ 24:0] avl_last_address_s; + wire [ 5:0] avl_wr_burstcount_s; + wire [ 5:0] avl_rd_burstcount_s; + wire [ 63:0] avl_wr_byteenable_s; + wire [ 63:0] avl_rd_byteenable_s; + wire avl_xfer_out_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s; + wire dac_xfer_fifo_out_s; + wire dac_dunf_fifo_s; + + avl_dacfifo_wr #( + .AVL_DATA_WIDTH (AVL_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS), + .DMA_MEM_ADDRESS_WIDTH(8) + ) i_wr ( + .dma_clk (dma_clk), + .dma_data (dma_data), + .dma_ready (dma_ready), + .dma_ready_out (dma_ready_wr_s), + .dma_valid (dma_valid), + .dma_xfer_req (dma_xfer_req), + .dma_xfer_last (dma_xfer_last), + .dma_last_beat (), + .avl_last_address (avl_last_address_s), + .avl_last_byteenable (), + .avl_clk (avl_clk), + .avl_reset (avl_reset), + .avl_address (avl_wr_address_s), + .avl_burstcount (avl_wr_burstcount_s), + .avl_byteenable (avl_wr_byteenable_s), + .avl_ready (avl_ready), + .avl_write (avl_write_s), + .avl_data (avl_writedata_s), + .avl_xfer_req (avl_xfer_out_s) + ); + + avl_dacfifo_rd #( + .AVL_DATA_WIDTH(AVL_DATA_WIDTH), + .DAC_DATA_WIDTH(DAC_DATA_WIDTH), + .AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS), + .AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT), + .DAC_MEM_ADDRESS_WIDTH(8) + ) i_rd ( + .dac_clk(dac_clk), + .dac_reset(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_fifo_s), + .dac_xfer_req(dac_xfer_fifo_out_s), + .dac_dunf(dac_dunf_fifo_s), + .avl_clk(avl_clk), + .avl_reset(avl_reset), + .avl_address(avl_rd_address_s), + .avl_burstcount(avl_rd_burstcount_s), + .avl_byteenable(avl_rd_byteenable_s), + .avl_ready(avl_ready), + .avl_readdatavalid(avl_readdata_valid), + .avl_read(avl_read_s), + .avl_data(avl_readdata), + .avl_last_address(avl_last_address_s), + .avl_last_byteenable(), + .avl_xfer_req(avl_xfer_out_s)); + + // avalon address multiplexer and output registers + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_address <= 0; + avl_burstcount <= 0; + avl_byteenable <= 0; + avl_read <= 0; + avl_write <= 0; + avl_writedata <= 0; + end else begin + avl_address <= (dma_xfer_req == 1'b1) ? avl_wr_address_s : avl_rd_address_s; + avl_burstcount <= (dma_xfer_req == 1'b1) ? avl_wr_burstcount_s : avl_rd_burstcount_s; + avl_byteenable <= (dma_xfer_req == 1'b1) ? avl_wr_byteenable_s : avl_rd_byteenable_s; + avl_read <= avl_read_s; + avl_write <= avl_write_s; + avl_writedata <= avl_writedata_s; + end + end + + // bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH + + generate + if (FIFO_BYPASS) begin + + util_dacfifo_bypass #( + .DAC_DATA_WIDTH (DAC_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH) + ) i_dacfifo_bypass ( + .dma_clk(dma_clk), + .dma_data(dma_data), + .dma_ready(dma_ready), + .dma_ready_out(dma_ready_bypass_s), + .dma_valid(dma_valid), + .dma_xfer_req(dma_xfer_req), + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_bypass_s), + .dac_dunf(dac_dunf_bypass_s) + ); + + always @(posedge dma_clk) begin + dma_bypass_m1 <= bypass; + dma_bypass <= dma_bypass_m1; + end + + always @(posedge dac_clk) begin + dac_bypass_m1 <= bypass; + dac_bypass <= dac_bypass_m1; + dac_xfer_out_m1 <= dma_xfer_req; + dac_xfer_out_bypass <= dac_xfer_out_m1; + end + + // mux for the dma_ready + + always @(posedge dma_clk) begin + dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s; + end + + // mux for dac data + + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s; + end + dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s; + dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s; + end + + end else begin /* if (~FIFO_BYPASS) */ + + always @(posedge dma_clk) begin + dma_ready <= dma_ready_wr_s; + end + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= dac_data_fifo_s; + end + dac_xfer_out <= dac_xfer_fifo_out_s; + dac_dunf <= dac_dunf_fifo_s; + end + + end + endgenerate + + +endmodule + diff --git a/library/altera/avl_dacfifo/avl_dacfifo_constr.sdc b/library/altera/avl_dacfifo/avl_dacfifo_constr.sdc new file mode 100644 index 000000000..10b929caf --- /dev/null +++ b/library/altera/avl_dacfifo/avl_dacfifo_constr.sdc @@ -0,0 +1,12 @@ +# CDC paths + +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|dac_mem_rd_address_g*] -to [get_registers *avl_dacfifo_rd:i_rd|avl_mem_rd_address_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_wr_address_g*] -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_wr_address_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_xfer_req*] -to [get_registers *avl_dacfifo_rd:i_rd|dac_avl_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_mem_raddr_g*] -to [get_registers *avl_dacfifo_wr:i_wr|dma_mem_raddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_write_xfer_req*] -to [get_registers *avl_dacfifo_wr:i_wr|dma_avl_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_read_control*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_mem_fetch_waddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_last_beat_ack*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_last_beat_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_last_beats*] -to [get_registers *avl_dacfifo_wr:i_wr|avl_last_beats_m1*] + diff --git a/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl b/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl new file mode 100644 index 000000000..8aff9e243 --- /dev/null +++ b/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl @@ -0,0 +1,63 @@ + +package require -exact qsys 13.0 +source ../../scripts/adi_env.tcl +source ../../scripts/adi_ip_alt.tcl + +ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo} +ad_ip_files avl_dacfifo [list\ + $ad_hdl_dir/library/common/ad_mem_asym.v \ + $ad_hdl_dir/library/common/util_dacfifo_bypass.v \ + avl_dacfifo_wr.v \ + avl_dacfifo_rd.v \ + avl_dacfifo.v \ + avl_dacfifo_constr.sdc] + +# parameters + +ad_ip_parameter DAC_DATA_WIDTH INTEGER 64 +ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 +ad_ip_parameter AVL_DATA_WIDTH INTEGER 512 +ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0 +ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000 + +# interfaces + +ad_alt_intf clock dma_clk input 1 clk +ad_alt_intf reset dma_rst input 1 if_dma_clk +ad_alt_intf signal dma_valid input 1 valid +ad_alt_intf signal dma_data input DMA_DATA_WIDTH data +ad_alt_intf signal dma_ready output 1 ready +ad_alt_intf signal dma_xfer_req input 1 xfer_req +ad_alt_intf signal dma_xfer_last input 1 last + +ad_alt_intf clock dac_clk input 1 clk +ad_alt_intf reset dac_rst input 1 if_dac_clk +ad_alt_intf signal dac_valid input 1 valid +ad_alt_intf signal dac_data output DAC_DATA_WIDTH data +ad_alt_intf signal dac_dunf output 1 unf +ad_alt_intf signal dac_xfer_out output 1 xfer_out + +ad_alt_intf signal bypass input 1 bypass + +add_interface avl_clock clock end +add_interface_port avl_clock avl_clk clk input 1 + +add_interface avl_reset reset end +set_interface_property avl_reset associatedclock avl_clock +add_interface_port avl_reset avl_reset reset input 1 + +add_interface amm_ddr avalon master +add_interface_port amm_ddr avl_address address output 25 +add_interface_port amm_ddr avl_burstcount burstcount output 7 +add_interface_port amm_ddr avl_byteenable byteenable output 64 +add_interface_port amm_ddr avl_read read output 1 +add_interface_port amm_ddr avl_readdata readdata input 512 +add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1 +add_interface_port amm_ddr avl_ready waitrequest_n input 1 +add_interface_port amm_ddr avl_write write output 1 +add_interface_port amm_ddr avl_writedata writedata output 512 + +set_interface_property amm_ddr associatedClock avl_clock +set_interface_property amm_ddr associatedReset avl_reset +set_interface_property amm_ddr addressUnits WORDS + diff --git a/library/altera/avl_dacfifo/avl_dacfifo_rd.v b/library/altera/avl_dacfifo/avl_dacfifo_rd.v new file mode 100644 index 000000000..f27639bc8 --- /dev/null +++ b/library/altera/avl_dacfifo/avl_dacfifo_rd.v @@ -0,0 +1,359 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_dacfifo_rd #( + + parameter AVL_DATA_WIDTH = 512, + parameter DAC_DATA_WIDTH = 64, + parameter AVL_DDR_BASE_ADDRESS = 0, + parameter AVL_DDR_ADDRESS_LIMIT = 1048576, + parameter DAC_MEM_ADDRESS_WIDTH = 8)( + + input dac_clk, + input dac_reset, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_xfer_req, + output reg dac_dunf, + + input avl_clk, + input avl_reset, + output reg [24:0] avl_address, + output reg [ 5:0] avl_burstcount, + output reg [63:0] avl_byteenable, + input avl_ready, + input avl_readdatavalid, + output reg avl_read, + input [AVL_DATA_WIDTH-1:0] avl_data, + + input [24:0] avl_last_address, + input [63:0] avl_last_byteenable, + input avl_xfer_req); + + // Max supported MEM_RATIO is 16 + localparam MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH; + localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) : + (DAC_MEM_ADDRESS_WIDTH - 4); + localparam AVL_MEM_THRESHOLD_LO = 8; + localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - 7; + + // internal register + + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address_g; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_m1; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_m2; + reg avl_mem_wr_enable; + reg avl_mem_request_data; + reg [AVL_DATA_WIDTH-1:0] avl_mem_data; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_address_diff; + reg avl_xfer_req_d; + reg avl_xfer_req_dd; + reg avl_read_inprogress; + + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address_m2; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address_m1; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_rd_address; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_rd_address_g; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_address_diff; + + reg dac_avl_xfer_req; + reg dac_avl_xfer_req_m1; + reg dac_avl_xfer_req_m2; + + // internal signals + + wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_s; + wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_address_diff_s; + wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_address_diff_s; + wire avl_xfer_req_init_s; + + wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_wr_address_s; + wire dac_mem_rd_enable_s; + wire [DAC_DATA_WIDTH-1:0] dac_mem_data_s; + + // ========================================================================== + // binary to grey conversion and grey to binary conversion for CDC circuitry + // ========================================================================== + + function [7:0] b2g; + input [7:0] b; + reg [7:0] g; + begin + g[7] = b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + + function [7:0] g2b; + input [7:0] g; + reg [7:0] b; + begin + b[7] = g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // ========================================================================== + // An asymmetric memory to transfer data from Avalon interface to DAC + // interface + // ========================================================================== + + ad_mem_asym #( + .A_ADDRESS_WIDTH (AVL_MEM_ADDRESS_WIDTH), + .A_DATA_WIDTH (AVL_DATA_WIDTH), + .B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH), + .B_DATA_WIDTH (DAC_DATA_WIDTH)) + i_mem_asym ( + .clka (avl_clk), + .wea (avl_mem_wr_enable), + .addra (avl_mem_wr_address), + .dina (avl_mem_data), + .clkb (dac_clk), + .addrb (dac_mem_rd_address), + .doutb (dac_mem_data_s)); + + // ========================================================================== + // Avalon Memory Mapped interface access + // ========================================================================== + + // Avalon address generation and read control signaling + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_address <= AVL_DDR_BASE_ADDRESS; + end else begin + if (avl_readdatavalid == 1'b1) begin + avl_address <= (avl_address < avl_last_address) ? avl_address + 1 : 0; + end + end + end + + assign avl_read_en_s = avl_xfer_req & avl_mem_request_data; + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_read <= 1'b0; + avl_read_inprogress <= 1'b0; + end else begin + if ((avl_read_inprogress == 1'b0) && (avl_read_en_s == 1'b1)) begin + avl_read <= 1'b1; + avl_read_inprogress <= 1'b1; + end else if (avl_read_inprogress == 1'b1) begin + avl_read <= 1'b0; + if (avl_readdatavalid == 1'b1) begin + avl_read_inprogress <= 1'b0; + end + end + end + end + + always @(posedge avl_clk) begin + avl_burstcount <= 1'b1; + avl_byteenable <= {64{1'b1}}; + end + + // write data from Avalon interface into the async FIFO + + assign avl_mem_wr_enable_s = avl_readdatavalid & avl_ready; + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_mem_data <= 0; + avl_mem_wr_enable <= 0; + end else begin + avl_mem_wr_enable <= avl_mem_wr_enable_s; + if (avl_mem_wr_enable_s == 1'b1) begin + avl_mem_data <= avl_data; + end + end + end + + always @(posedge avl_clk) begin + avl_xfer_req_d <= avl_xfer_req; + avl_xfer_req_dd <= avl_xfer_req_d; + end + assign avl_xfer_req_init_s = avl_xfer_req_d & ~avl_xfer_req_dd; + + always @(posedge avl_clk) begin + if ((avl_reset == 1'b1) || (avl_xfer_req_init_s == 1'b1)) begin + avl_mem_wr_address <= 0; + avl_mem_wr_address_g <= 0; + end else begin + if (avl_mem_wr_enable == 1'b1) begin + avl_mem_wr_address <= avl_mem_wr_address + 1; + end + avl_mem_wr_address_g <= b2g(avl_mem_wr_address); + end + end + + // ========================================================================== + // control the FIFO to prevent overflow, underfloq is monitored + // ========================================================================== + + assign avl_mem_rd_address_s = (MEM_RATIO == 1) ? avl_mem_rd_address : + (MEM_RATIO == 2) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):1] : + (MEM_RATIO == 4) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):2] : + (MEM_RATIO == 8) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):3] : + avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):4]; + + assign avl_mem_address_diff_s = {1'b1, avl_mem_wr_address} - avl_mem_rd_address_s; + + always @(posedge avl_clk) begin + if (avl_xfer_req == 1'b0) begin + avl_mem_address_diff <= 'd0; + avl_mem_rd_address <= 'd0; + avl_mem_rd_address_m1 <= 'd0; + avl_mem_rd_address_m2 <= 'd0; + avl_mem_request_data <= 'd0; + end else begin + avl_mem_rd_address_m1 <= dac_mem_rd_address_g; + avl_mem_rd_address_m2 <= avl_mem_rd_address_m1; + avl_mem_rd_address <= g2b(avl_mem_rd_address_m2); + avl_mem_address_diff <= avl_mem_address_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0]; + if (avl_mem_address_diff >= AVL_MEM_THRESHOLD_HI) begin + avl_mem_request_data <= 1'b0; + end else if (avl_mem_address_diff <= AVL_MEM_THRESHOLD_LO) begin + avl_mem_request_data <= 1'b1; + end + end + end + + // ========================================================================== + // Push data from the async FIFO to the DAC + // Data flow is controlled by the DAC, no back-pressure. If FIFO is not + // ready, data will be dropped + // ========================================================================== + + assign dac_mem_wr_address_s = (MEM_RATIO == 1) ? dac_mem_wr_address : + (MEM_RATIO == 2) ? {dac_mem_wr_address, 1'b0} : + (MEM_RATIO == 4) ? {dac_mem_wr_address, 2'b0} : + (MEM_RATIO == 8) ? {dac_mem_wr_address, 3'b0} : + {dac_mem_wr_address, 4'b0}; + + assign dac_mem_address_diff_s = {1'b1, dac_mem_wr_address_s} - dac_mem_rd_address; + + always @(posedge dac_clk) begin + if (dac_reset == 1'b1) begin + dac_mem_wr_address_m2 <= 0; + dac_mem_wr_address_m1 <= 0; + dac_mem_wr_address <= 0; + end else begin + dac_mem_wr_address_m1 <= avl_mem_wr_address_g; + dac_mem_wr_address_m2 <= dac_mem_wr_address_m1; + dac_mem_wr_address <= g2b(dac_mem_wr_address_m2); + end + end + + always @(posedge dac_clk) begin + if (dac_reset == 1'b1) begin + dac_avl_xfer_req_m2 <= 0; + dac_avl_xfer_req_m1 <= 0; + dac_avl_xfer_req <= 0; + end else begin + dac_avl_xfer_req_m1 <= avl_xfer_req; + dac_avl_xfer_req_m2 <= dac_avl_xfer_req_m1; + dac_avl_xfer_req <= dac_avl_xfer_req_m1; + end + end + + assign dac_mem_rd_enable_s = (dac_xfer_req == 1'b1) ? dac_valid : 0; + always @(posedge dac_clk) begin + if ((dac_reset == 1'b1) || ((dac_avl_xfer_req == 1'b0) && (dac_xfer_req == 1'b0))) begin + dac_mem_rd_address <= 0; + dac_mem_rd_address_g <= 0; + dac_mem_address_diff <= 0; + end else begin + dac_mem_address_diff <= dac_mem_address_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0]; + if (dac_mem_rd_enable_s == 1'b1) begin + dac_mem_rd_address <= dac_mem_rd_address + 1; + end + dac_mem_rd_address_g <= b2g(dac_mem_rd_address); + end + end + + always @(posedge dac_clk) begin + if (dac_reset == 1'b1) begin + dac_xfer_req <= 0; + end else begin + if ((dac_avl_xfer_req == 1'b1) && (dac_mem_address_diff > 0)) begin + dac_xfer_req <= 1'b1; + end else if ((dac_avl_xfer_req == 1'b0) && (dac_mem_address_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0] == 0)) begin + dac_xfer_req <= 1'b0; + end + end + end + + always @(posedge dac_clk) begin + if ((dac_reset == 1'b1) || (dac_xfer_req == 1'b0)) begin + dac_data <= 0; + end else begin + dac_data <= dac_mem_data_s; + end + end + + always @(posedge dac_clk) begin + if ((dac_reset == 1'b1) || (dac_xfer_req == 1'b0)) begin + dac_dunf <= 1'b0; + end else begin + dac_dunf <= (dac_mem_address_diff == 0) ? 1'b1 : 1'b0; + end + end + +endmodule + diff --git a/library/altera/avl_dacfifo/avl_dacfifo_wr.v b/library/altera/avl_dacfifo/avl_dacfifo_wr.v new file mode 100644 index 000000000..1dd89c937 --- /dev/null +++ b/library/altera/avl_dacfifo/avl_dacfifo_wr.v @@ -0,0 +1,509 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_dacfifo_wr #( + + parameter AVL_DATA_WIDTH = 512, + parameter DMA_DATA_WIDTH = 64, + parameter AVL_DDR_BASE_ADDRESS = 0, + parameter AVL_DDR_ADDRESS_LIMIT = 1048576, + parameter DMA_MEM_ADDRESS_WIDTH = 8)( + + input dma_clk, + input [DMA_DATA_WIDTH-1:0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, + input dma_xfer_req, + input dma_xfer_last, + output reg [ 3:0] dma_last_beat, + + input avl_clk, + input avl_reset, + output reg [24:0] avl_address, + output reg [ 5:0] avl_burstcount, + output reg [63:0] avl_byteenable, + input avl_ready, + output reg avl_write, + output reg [AVL_DATA_WIDTH-1:0] avl_data, + + output reg [24:0] avl_last_address, + output reg [63:0] avl_last_byteenable, + output reg avl_xfer_req); + + localparam MEM_RATIO = AVL_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16 + localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : + (DMA_MEM_ADDRESS_WIDTH - 4); + localparam MEM_WIDTH_DIFF = (MEM_RATIO > 8) ? 4 : + (MEM_RATIO > 4) ? 3 : + (MEM_RATIO > 2) ? 2 : + (MEM_RATIO > 1) ? 1 : 1; + + localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4; + localparam DMA_BYTE_DATA_WIDTH = DMA_DATA_WIDTH/8; + localparam AVL_BYTE_DATA_WIDTH = AVL_DATA_WIDTH/8; + + wire dma_resetn; + wire dma_mem_wea_s; + wire [DMA_MEM_ADDRESS_WIDTH :0] dma_mem_address_diff_s; + wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_s; + + wire [AVL_DATA_WIDTH-1:0] avl_mem_rdata_s; + wire avl_mem_fetch_wr_address_s; + wire avl_mem_readen_s; + wire avl_write_transfer_s; + wire avl_last_transfer_req; + wire avl_xfer_req_init_s; + wire avl_write_transfer_done_s; + + reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_wr_address; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_wr_address_d; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_m1; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_m2; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address; + reg dma_mem_read_control; + reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_address_diff; + reg dma_last_beat_ack; + reg [MEM_WIDTH_DIFF-1:0] dma_mem_last_beats; + reg dma_avl_xfer_req_m1; + reg dma_avl_xfer_req; + + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_g; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address_next; + reg avl_mem_fetch_wr_address; + reg avl_mem_fetch_wr_address_m1; + reg avl_mem_fetch_wr_address_m2; + reg avl_write_d; + reg avl_mem_readen; + reg avl_write_transfer; + reg avl_last_beat_req_m1; + reg avl_last_beat_req; + reg avl_dma_xfer_req; + reg avl_dma_xfer_req_m1; + reg avl_dma_xfer_req_m2; + reg [MEM_WIDTH_DIFF-1:0] avl_last_beats; + reg [MEM_WIDTH_DIFF-1:0] avl_last_beats_m1; + reg [MEM_WIDTH_DIFF-1:0] avl_last_beats_m2; + reg avl_write_xfer_req; + + // binary to grey conversion + + function [7:0] b2g; + input [7:0] b; + reg [7:0] g; + begin + g[7] = b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + // grey to binary conversion + + function [7:0] g2b; + input [7:0] g; + reg [7:0] b; + begin + b[7] = g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // An asymmetric memory to transfer data from DMAC interface to AXI Memory Map + // interface + + ad_mem_asym #( + .A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH), + .A_DATA_WIDTH (DMA_DATA_WIDTH), + .B_ADDRESS_WIDTH (AVL_MEM_ADDRESS_WIDTH), + .B_DATA_WIDTH (AVL_DATA_WIDTH)) + i_mem_asym ( + .clka (dma_clk), + .wea (dma_mem_wea_s), + .addra (dma_mem_wr_address), + .dina (dma_data), + .clkb (avl_clk), + .addrb (avl_mem_rd_address), + .doutb (avl_mem_rdata_s)); + + // the fifo reset is the dma_xfer_req + + assign dma_resetn = dma_xfer_req; + + // write address generation + + assign dma_mem_address_diff_s = {1'b1, dma_mem_wr_address} - dma_mem_rd_address_s; + assign dma_mem_rd_address_s = (MEM_RATIO == 1) ? dma_mem_rd_address : + (MEM_RATIO == 2) ? {dma_mem_rd_address, 1'b0} : + (MEM_RATIO == 4) ? {dma_mem_rd_address, 2'b0} : + (MEM_RATIO == 8) ? {dma_mem_rd_address, 3'b0} : + {dma_mem_rd_address, 4'b0}; + assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req; + + always @(posedge dma_clk) begin + if (dma_resetn == 1'b0) begin + dma_mem_wr_address <= 0; + dma_mem_read_control <= 1'b0; + dma_mem_last_beats <= 0; + end else begin + if (dma_mem_wea_s == 1'b1) begin + dma_mem_wr_address <= dma_mem_wr_address + 1; + end + if (dma_mem_wr_address[MEM_WIDTH_DIFF-1:0] == {MEM_WIDTH_DIFF{1'b1}}) begin + dma_mem_read_control <= ~dma_mem_read_control; + dma_mem_wr_address_d <= dma_mem_wr_address[DMA_MEM_ADDRESS_WIDTH-1:MEM_WIDTH_DIFF]; + end + end + if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s)) begin + dma_mem_last_beats <= dma_mem_wr_address[MEM_WIDTH_DIFF-1:0]; + end + end + + // The memory module request data until reaches the high threshold. + + always @(posedge dma_clk) begin + if (dma_resetn == 1'b0) begin + dma_mem_address_diff <= 'b0; + dma_mem_rd_address_m1 <= 'b0; + dma_mem_rd_address_m2 <= 'b0; + dma_mem_rd_address <= 'b0; + dma_ready_out <= 1'b0; + end else begin + dma_mem_rd_address_m1 <= avl_mem_rd_address_g; + dma_mem_rd_address_m2 <= dma_mem_rd_address_m1; + dma_mem_rd_address <= g2b(dma_mem_rd_address_m2); + dma_mem_address_diff <= dma_mem_address_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0]; + if (dma_mem_address_diff >= DMA_BUF_THRESHOLD_HI) begin + dma_ready_out <= 1'b0; + end else begin + dma_ready_out <= 1'b1; + end + end + end + + // last DMA beat + + always @(posedge dma_clk) begin + dma_avl_xfer_req_m1 <= avl_write_xfer_req; + dma_avl_xfer_req <= dma_avl_xfer_req_m1; + end + + always @(posedge dma_clk) begin + if (dma_avl_xfer_req == 1'b0) begin + dma_last_beat_ack <= 1'b0; + end else begin + if ((dma_xfer_req == 1'b1) && (dma_xfer_last == 1'b1)) begin + dma_last_beat_ack <= 1'b1; + end + end + end + + // transfer the mem_write address to the avalons clock domain + + assign avl_mem_fetch_wr_address_s = avl_mem_fetch_wr_address ^ avl_mem_fetch_wr_address_m1; + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_mem_fetch_wr_address_m1 <= 0; + avl_mem_fetch_wr_address_m2 <= 0; + avl_mem_fetch_wr_address <= 0; + avl_mem_wr_address <= 0; + avl_mem_wr_address_next <= 0; + end else begin + avl_mem_fetch_wr_address_m1 <= dma_mem_read_control; + avl_mem_fetch_wr_address_m2 <= avl_mem_fetch_wr_address_m1; + avl_mem_fetch_wr_address <= avl_mem_fetch_wr_address_m2; + if (avl_mem_fetch_wr_address_s == 1'b1) begin + avl_mem_wr_address <= dma_mem_wr_address_d; + avl_mem_wr_address_next <= avl_mem_wr_address + 1; + end + end + end + + // Avalon write address and fifo read address generation + + assign avl_mem_readen_s = (avl_mem_rd_address == avl_mem_wr_address_next) ? 0 : avl_write_xfer_req; + assign avl_write_transfer_s = avl_write & avl_ready; + assign avl_write_transfer_done_s = avl_write_transfer & ~avl_write_transfer_s; + + always @(posedge avl_clk) begin + if ((avl_reset == 1'b1) || (avl_write_xfer_req == 1'b0)) begin + avl_address <= AVL_DDR_BASE_ADDRESS; + avl_data <= 0; + avl_write_transfer <= 1'b0; + avl_mem_readen <= 0; + avl_mem_rd_address <= 0; + avl_mem_rd_address_g <= 0; + end else begin + if (avl_write_transfer_done_s == 1'b1) begin + avl_address <= (avl_address < AVL_DDR_ADDRESS_LIMIT) ? avl_address + 1 : 0; + end + if (avl_write_transfer_s == 1'b1) begin + avl_mem_rd_address <= avl_mem_rd_address + 1; + end + avl_data <= avl_mem_rdata_s; + avl_mem_rd_address_g <= b2g(avl_mem_rd_address); + avl_write_transfer <= avl_write_transfer_s; + avl_mem_readen <= avl_mem_readen_s; + end + end + + // avalon write signaling + + assign avl_last_transfer_req = avl_last_beat_req & ~avl_mem_readen; + + always @(negedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_write <= 1'b0; + avl_write_d <= 1'b0; + end else begin + if ((((avl_mem_readen == 1'b1) && (avl_write_xfer_req == 1'b1)) || + ((avl_last_transfer_req == 1'b1) && (avl_write_xfer_req == 1'b1))) && + (avl_write == 1'b0) && (avl_write_d == 1'b0)) begin + avl_write <= 1'b1; + end else if (avl_write_transfer == 1'b1) begin + avl_write <= 1'b0; + end + avl_write_d <= avl_write; + end + end + + assign avl_xfer_req_init_s = ~avl_dma_xfer_req & avl_dma_xfer_req_m2; + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_last_beat_req_m1 <= 1'b0; + avl_last_beat_req <= 1'b0; + avl_write_xfer_req <= 1'b0; + avl_dma_xfer_req_m1 <= 1'b0; + avl_dma_xfer_req_m2 <= 1'b0; + avl_dma_xfer_req <= 1'b0; + end else begin + avl_last_beat_req_m1 <= dma_last_beat_ack; + avl_last_beat_req <= avl_last_beat_req_m1; + avl_dma_xfer_req_m1 <= dma_xfer_req; + avl_dma_xfer_req_m2 <= avl_dma_xfer_req_m1; + avl_dma_xfer_req <= avl_dma_xfer_req_m2; + if (avl_xfer_req_init_s == 1'b1) begin + avl_write_xfer_req <= 1'b1; + end else if ((avl_last_transfer_req == 1'b1) && + (avl_write_transfer == 1'b1)) begin + avl_write_xfer_req <= 1'b0; + end + end + end + + // generate avl_byteenable signal + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_last_beats_m1 <= 1'b0; + avl_last_beats_m2 <= 1'b0; + avl_last_beats <= 1'b0; + end else begin + avl_last_beats_m1 <= dma_mem_last_beats; + avl_last_beats_m2 <= avl_last_beats_m1; + avl_last_beats <= (avl_last_beat_req == 1'b1) ? avl_last_beats_m2 : avl_last_beats; + end + end + + always @(posedge avl_clk) begin + if (avl_last_transfer_req == 1'b1) begin + case (avl_last_beats) + 0 : begin + case (MEM_RATIO) + 2 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 4 : avl_byteenable <= {48'b0, {16{1'b1}}}; + 8 : avl_byteenable <= {56'b0, {8{1'b1}}}; + 16 : avl_byteenable <= {60'b0, {4{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 1 : begin + case (MEM_RATIO) + 4 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 8 : avl_byteenable <= {48'b0, {16{1'b1}}}; + 16 : avl_byteenable <= {56'b0, {8{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 2 : begin + case (MEM_RATIO) + 4 : avl_byteenable <= {16'b0, {48{1'b1}}}; + 8 : avl_byteenable <= {40'b0, {24{1'b1}}}; + 16 : avl_byteenable <= {52'b0, {12{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 3 : begin + case (MEM_RATIO) + 8 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 16 : avl_byteenable <= {48'b0, {16{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 4 : begin + case (MEM_RATIO) + 8 : avl_byteenable <= {24'b0, {40{1'b1}}}; + 16 : avl_byteenable <= {44'b0, {20{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 5 : begin + case (MEM_RATIO) + 8 : avl_byteenable <= {16'b0, {48{1'b1}}}; + 16 : avl_byteenable <= {40'b0, {24{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 6 : begin + case (MEM_RATIO) + 8 : avl_byteenable <= {8'b0, {56{1'b1}}}; + 16 : avl_byteenable <= {36'b0, {28{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 7 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {32'b0, {32{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 8 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {28'b0, {36{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 9 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {24'b0, {40{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 10 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {20'b0, {44{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 11 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {16'b0, {48{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 12 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {12'b0, {52{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 13 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {8'b0, {56{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 14 : begin + case (MEM_RATIO) + 16 : avl_byteenable <= {4'b0, {60{1'b1}}}; + default : avl_byteenable <= {64{1'b1}}; + endcase + end + 15 : begin + avl_byteenable <= {64{1'b1}}; + end + default : avl_byteenable <= {64{1'b1}}; + endcase + end else begin + avl_byteenable <= {64{1'b1}}; + end + avl_burstcount <= 6'b1; + end + + // save the last address and byteenable + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_last_address <= 0; + avl_last_byteenable <= 0; + end else begin + if ((avl_write == 1'b1) && (avl_last_transfer_req == 1'b1)) begin + avl_last_address <= avl_address; + avl_last_byteenable <= avl_byteenable; + end + end + end + + // avl_xfer_req generation for synchronize the access of the external + // memory + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_xfer_req <= 1'b0; + end else begin + if ((avl_last_transfer_req == 1'b1) && + (avl_write_transfer == 1'b1)) begin + avl_xfer_req <= 1'b1; + end else if ((avl_xfer_req == 1'b1) && (avl_dma_xfer_req == 1'b1)) begin + avl_xfer_req <= 1'b0; + end + end + end + +endmodule