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cpack- signaltap mess

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Rejeesh Kutty 2015-06-29 16:31:53 -04:00
parent 6bc24e25eb
commit 185e489802
3 changed files with 6 additions and 22 deletions
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17
library/common/altera/sld_signaltap.v → library/common/altera/system_stap.v
View File

@ -37,26 +37,17 @@
`timescale 1ps/1ps
module sld_signaltap (
module system_stap (
acq_clk,
acq_trigger_in,
acq_data_in);
// parameters
parameter sld_sample_depth = 1024;
parameter sld_data_bits = 32;
parameter sld_trigger_bits = 1;
parameter sld_trigger_level = 1;
parameter sld_trigger_in_enabled = 0;
parameter sld_enable_advanced_trigger = 0;
// data interface
input acq_clk;
input [(sld_trigger_bits-1):0] acq_trigger_in;
input [(sld_data_bits-1):0] acq_data_in;
input acq_clk;
input acq_trigger_in;
input acq_data_in;
endmodule

9
library/util_cpack/util_cpack.v
View File

@ -174,14 +174,7 @@ module util_cpack (
generate
if (ST_DEPTH > 0) begin
sld_signaltap #(
.sld_sample_depth (ST_DEPTH),
.sld_data_bits (CH_CNT*CH_DW),
.sld_trigger_bits (1),
.sld_trigger_level (1),
.sld_trigger_in_enabled (0),
.sld_enable_advanced_trigger (0))
i_st (
system_stap i_st (
.acq_clk (adc_clk),
.acq_trigger_in (adc_valid_d),
.acq_data_in (adc_data_d[((CH_CNT*CH_DW)-1):0]));

2
library/util_cpack/util_cpack_ip.tcl
View File

@ -5,7 +5,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_cpack
adi_ip_files util_cpack [list \
"$ad_hdl_dir/library/common/altera/sld_signaltap.v" \
"$ad_hdl_dir/library/common/altera/system_stap.v" \
"util_cpack_mux.v" \
"util_cpack_dsf.v" \
"util_cpack.v" \