zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad7606x_fmc: Initial commit

main
alin724 2022-10-27 21:35:12 +03:00 committed by Alin-Tudor Sferle
parent cd448ea0d0
commit 189624a655
9 changed files with 513 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
projects/ad7606x_fmc/Makefile Normal file
View File

@ -0,0 +1,7 @@
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

21
projects/ad7606x_fmc/Readme.md Normal file
View File

@ -0,0 +1,21 @@
# AD7606X-FMC HDL Project
Here are some pointers to help you:
* [EVAL-AD7606B Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7606b-fmcz.html)
* [EVAL-AD7606C-16/18 Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7606c-18.html)
* Parts : AD7606B [8 Channels, 16-bit, 800 kSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606b.html)
* Parts : AD7606C-16 [8 Channels, 16-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-16.html)
* Parts : AD7606B [8 Channels, 18-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-18.html)
* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmcz
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl
## Building, Generating Bit Files
IMPORTANT: Set AD7606X device model, ADC Read Mode option and external clock option
How to use over-writable parameters from the environment:
```
hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=0 SIMPLE_STATUS_CRC=0
DEV_CONFIG - Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
SIMPLE_STATUS_CRC - Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS.
EXT_CLK - Defines the external clock option for the ADC clock: 0 - No, 1 - Yes.

124
projects/ad7606x_fmc/common/ad7606x_bd.tcl Normal file
View File

@ -0,0 +1,124 @@
# system level parameters
set DEV_CONFIG $ad_project_params(DEV_CONFIG)
set ADC_N_BITS [expr {$DEV_CONFIG == 2 ? 18 : 16}]
set ADC_TO_DMA_N_BITS [expr {$ADC_N_BITS == 16 ? 16 : 32}]
set SIMPLE_STATUS_CRC $ad_project_params(SIMPLE_STATUS_CRC)
set EXT_CLK $ad_project_params(EXT_CLK)
set TOTAL_N_BITS_DMA [expr {$ADC_TO_DMA_N_BITS*8}]
puts "build parameters: DEV_CONFIG: $DEV_CONFIG"
puts "build parameters: SIMPLE_STATUS_CRC: $SIMPLE_STATUS_CRC"
puts "build parameters: EXT_CLK: $EXT_CLK"
# data, read and write lines
create_bd_port -dir O -from 15 -to 0 rx_db_o
create_bd_port -dir I -from 15 -to 0 rx_db_i
create_bd_port -dir O rx_db_t
create_bd_port -dir O rx_rd_n
create_bd_port -dir O rx_wr_n
# control lines
create_bd_port -dir I rx_busy
create_bd_port -dir O rx_cnvst_n
create_bd_port -dir O rx_cs_n
create_bd_port -dir I rx_first_data
# instantiation
ad_ip_instance axi_ad7606x axi_ad7606x
ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
ad_ip_parameter axi_ad7606x CONFIG.ADC_N_BITS $ADC_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.ADC_TO_DMA_N_BITS $ADC_TO_DMA_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.ADC_READ_MODE $SIMPLE_STATUS_CRC
ad_ip_parameter axi_ad7606x CONFIG.EXTERNAL_CLK $EXT_CLK
ad_ip_instance axi_pwm_gen axi_pwm_gen
ad_ip_parameter axi_pwm_gen CONFIG.ASYNC_CLK_EN 0
ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 1
if {$DEV_CONFIG == 0} {
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 124
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 125
} else {
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 99
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 100
}
ad_ip_instance axi_dmac axi_ad7606x_dma
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7606x_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_SRC $TOTAL_N_BITS_DMA
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_cpack2 ad7606x_adc_pack
ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_N_BITS
if {$EXT_CLK == 1} {
# use Xilinx's clocking wizard in order to generate th clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP
ad_ip_instance clk_wiz adc_clk_generator
ad_ip_parameter adc_clk_generator CONFIG.PRIMITIVE PLL
ad_ip_parameter adc_clk_generator CONFIG.RESET_TYPE ACTIVE_LOW
ad_ip_parameter adc_clk_generator CONFIG.USE_LOCKED false
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100.000
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_PHASE 0.000
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000
ad_ip_parameter adc_clk_generator CONFIG.PRIM_SOURCE Global_buffer
ad_ip_parameter adc_clk_generator CONFIG.CLKIN1_UI_JITTER 0
ad_ip_parameter adc_clk_generator CONFIG.PRIM_IN_FREQ 100.000
ad_connect sys_cpu_clk adc_clk_generator/clk_in1
ad_connect sys_cpu_resetn adc_clk_generator/resetn
ad_connect adc_clk_generator/clk_out1 axi_ad7606x/external_clk
} else {
ad_connect sys_cpu_clk axi_ad7606x/external_clk
}
# interface connections
ad_connect rx_db_o axi_ad7606x/rx_db_o
ad_connect rx_db_i axi_ad7606x/rx_db_i
ad_connect rx_db_t axi_ad7606x/rx_db_t
ad_connect rx_rd_n axi_ad7606x/rx_rd_n
ad_connect rx_wr_n axi_ad7606x/rx_wr_n
ad_connect rx_cs_n axi_ad7606x/rx_cs_n
ad_connect rx_cnvst_n axi_pwm_gen/pwm_0
ad_connect rx_busy axi_ad7606x/rx_busy
ad_connect rx_first_data axi_ad7606x/first_data
ad_connect sys_cpu_clk axi_ad7606x_dma/s_axi_aclk
ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk
ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn
ad_connect axi_ad7606x/adc_clk ad7606x_adc_pack/clk
ad_connect axi_ad7606x/adc_clk axi_ad7606x_dma/fifo_wr_clk
ad_connect axi_ad7606x/adc_reset ad7606x_adc_pack/reset
ad_connect axi_ad7606x/adc_valid ad7606x_adc_pack/fifo_wr_en
ad_connect ad7606x_adc_pack/packed_fifo_wr axi_ad7606x_dma/fifo_wr
ad_connect ad7606x_adc_pack/fifo_wr_overflow axi_ad7606x/adc_dovf
for {set i 0} {$i < 8} {incr i} {
ad_connect axi_ad7606x/adc_data_$i ad7606x_adc_pack/fifo_wr_data_$i
ad_connect axi_ad7606x/adc_enable_$i ad7606x_adc_pack/enable_$i
}
# interconnect
ad_cpu_interconnect 0x44A00000 axi_ad7606x
ad_cpu_interconnect 0x44A30000 axi_ad7606x_dma
ad_cpu_interconnect 0x44A60000 axi_pwm_gen
# memory interconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad7606x_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad7606x_dma/m_dest_axi_aresetn
#interrupt
ad_cpu_interrupt ps-13 mb-12 axi_ad7606x_dma/irq

34
projects/ad7606x_fmc/common/ad7606x_fmc.txt Normal file
View File

@ -0,0 +1,34 @@
FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
# ad7606x
D08 LA01_CC_P DB0_1 adc_db[0] LVCMOS25 #N/A
D09 LA01_CC_N DB1_1 adc_db[1] LVCMOS25 #N/A
H08 LA02_N DB2_1 adc_db[2] LVCMOS25 #N/A
G10 LA03_N DB3_1 adc_db[3] LVCMOS25 #N/A
H11 LA04_N DB4_1 adc_db[4] LVCMOS25 #N/A
H14 LA07_N DB5_1 adc_db[5] LVCMOS25 #N/A
G13 LA08_N DB6_1 adc_db[6] LVCMOS25 #N/A
G07 LA00_CC_N DOUTA_1 adc_db[7] LVCMOS25 #N/A
C11 LA06_N DOUTB_1 adc_db[8] LVCMOS25 #N/A
D11 LA05_P DOUTC_1 adc_db[9] LVCMOS25 #N/A
D14 LA09_P DOUTD_1 adc_db[10] LVCMOS25 #N/A
G09 LA03_P SDI_1 adc_db[11] LVCMOS25 #N/A
H17 LA11_N DB12_1 adc_db[12] LVCMOS25 #N/A
G16 LA12_N DB13_1 adc_db[13] LVCMOS25 #N/A
D17 LA13_P DB14_1 adc_db[14] LVCMOS25 #N/A
D18 LA13_N DB15_1 adc_db[15] LVCMOS25 #N/A
G06 LA00_CC_P SCLK_1 adc_rd_n LVCMOS25 #N/A
C14 LA10_P WR_SDP adc_wr_n LVCMOS25 #N/A
H13 LA07_P BUSY_SDP adc_busy LVCMOS25 #N/A
D12 LA05_N CNVST_SDP adc_cnvst_n LVCMOS25 #N/A
H10 LA04_P CS_1 adc_cs_n LVCMOS25 #N/A
G12 LA08_P FRSTDATA_SDP adc_first_data LVCMOS25 #N/A
C10 LA06_P RESET_1 adc_reset LVCMOS25 #N/A
G15 LA12_P OS0 adc_os[0] LVCMOS25 #N/A
H07 LA04_P OS1 adc_os[1] LVCMOS25 #N/A
H16 LA11_P OS2 adc_os[2] LVCMOS25 #N/A
C15 LA10_N STBY adc_stby LVCMOS25 #N/A
D15 LA09_N RANGE_1 adc_range LVCMOS25 #N/A

28
projects/ad7606x_fmc/zed/Makefile Normal file
View File

@ -0,0 +1,28 @@
####################################################################################
## Copyright (c) 2018 - 2022 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7606x_fmc_zed
M_DEPS += system_constr.xdc
M_DEPS += ../common/ad7606x_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
LIB_DEPS += axi_ad7606x
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_pwm_gen
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pack/util_cpack2
include ../../scripts/project-xilinx.mk

13
projects/ad7606x_fmc/zed/system_bd.tcl Normal file
View File

@ -0,0 +1,13 @@
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
source ../common/ad7606x_bd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "$DEV_CONFIG,$SIMPLE_STATUS_CRC,$EXT_CLK"
sysid_gen_sys_init_file $sys_cstring

34
projects/ad7606x_fmc/zed/system_constr.xdc Normal file
View File

@ -0,0 +1,34 @@
# ad7606x
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## C14 FMC_LPC_LA10_P
# control lines
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst_n] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports adc_first_data] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_reset] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## H07 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_stby] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_range] ; ## D15 FMC_LPC_LA09_N

30
projects/ad7606x_fmc/zed/system_project.tcl Normal file
View File

@ -0,0 +1,30 @@
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
# Parameter description
# DEV_CONFIG - The device which will be used
# - Options : AD7606B(0)/C-16(1)/C-18(2)
# SIMPLE_STATUS_CRC - ADC read mode options
# - Options : SIMPLE(0), STATUS(1), CRC(2) CRC_STATUS(3)
# EXT_CLK - Use external clock as ADC clock
# - Options : No(0), Yes(1)
set DEV_CONFIG [get_env_param DEV_CONFIG 0]
set SIMPLE_STATUS_CRC [get_env_param SIMPLE_STATUS_CRC 0]
set EXT_CLK [get_env_param EXT_CLK 0]
adi_project ad7606x_fmc_zed 0 [list \
DEV_CONFIG $DEV_CONFIG \
SIMPLE_STATUS_CRC $SIMPLE_STATUS_CRC \
EXT_CLK $EXT_CLK \
]
adi_project_files ad7606x_fmc_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"system_top.v" \
"system_constr.xdc"]
adi_project_run ad7606x_fmc_zed

222
projects/ad7606x_fmc/zed/system_top.v Normal file
View File

@ -0,0 +1,222 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
inout [15:0] adc_db,
output adc_rd_n,
output adc_wr_n,
input adc_busy,
output adc_cnvst_n,
output adc_cs_n,
input adc_first_data,
output adc_reset,
output [2:0] adc_os,
output adc_stby,
output adc_range
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;
// instantiations
ad_iobuf #(
.DATA_WIDTH(6)
) i_iobuf_adc_cntrl (
.dio_t (gpio_t[37:32]),
.dio_i (gpio_o[37:32]),
.dio_o (gpio_i[37:32]),
.dio_p ({adc_reset, // 37
adc_stby, // 36
adc_range, // 35
adc_os})); // 34:32
assign gpio_i[63:38] = gpio_o[63:38];
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.rx_busy (adc_busy),
.rx_cnvst_n (adc_cnvst_n),
.rx_cs_n (adc_cs_n),
.rx_db_i (adc_db_i),
.rx_db_o (adc_db_o),
.rx_db_t (adc_db_t),
.rx_first_data (adc_first_data),
.rx_rd_n (adc_rd_n),
.rx_wr_n (adc_wr_n));
endmodule