From 18a506b3ca6f827787201ff70ef100fffea618ca Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 10 Sep 2014 12:39:01 +0200 Subject: [PATCH] up_axi: Wait for the transaction to fully finish before releasing up_axi_access Wait for the master to accept the response for the current transaction before we allow a new transaction to start. This fixes problems in case the master is not ready to accept the response when we make it available. Signed-off-by: Lars-Peter Clausen --- library/common/up_axi.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/library/common/up_axi.v b/library/common/up_axi.v index bc630f52a..bf1841c5f 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -136,6 +136,7 @@ module up_axi ( wire up_axi_wr_s; wire up_axi_rd_s; + wire up_axi_ack_s; wire [31:0] up_rdata_s; wire up_ack_s; @@ -152,6 +153,9 @@ module up_axi ( assign up_axi_rd_s = ((up_axi_araddr >= PCORE_BASEADDR) && (up_axi_araddr <= PCORE_HIGHADDR)) ? (up_axi_arvalid & ~up_axi_access) : 1'b0; + assign up_axi_ack_s = ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) || + ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)); + // return address and data channel ready right away, response depends on ack always @(negedge up_rstn or posedge up_clk) begin @@ -202,7 +206,7 @@ module up_axi ( up_wdata <= 'd0; end else begin if (up_axi_access == 1'b1) begin - if (up_ack_s == 1'b1) begin + if (up_axi_ack_s == 1'b1) begin up_axi_access <= 1'b0; end up_sel <= 1'b0;