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up_axi: Wait for the transaction to fully finish before releasing up_axi_access 

Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.

This fixes problems in case the master is not ready to accept the response
when we make it available.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-10 12:39:01 +02:00
parent 0da7b6eaa1
commit 18a506b3ca
1 changed files with 5 additions and 1 deletions
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6
library/common/up_axi.v
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@ -136,6 +136,7 @@ module up_axi (
wire up_axi_wr_s; wire up_axi_wr_s;
wire up_axi_rd_s; wire up_axi_rd_s;
wire up_axi_ack_s;
wire [31:0] up_rdata_s; wire [31:0] up_rdata_s;
wire up_ack_s; wire up_ack_s;
@ -152,6 +153,9 @@ module up_axi (
assign up_axi_rd_s = ((up_axi_araddr >= PCORE_BASEADDR) && (up_axi_araddr <= PCORE_HIGHADDR)) ? assign up_axi_rd_s = ((up_axi_araddr >= PCORE_BASEADDR) && (up_axi_araddr <= PCORE_HIGHADDR)) ?
(up_axi_arvalid & ~up_axi_access) : 1'b0; (up_axi_arvalid & ~up_axi_access) : 1'b0;
assign up_axi_ack_s = ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) ||
((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1));
// return address and data channel ready right away, response depends on ack // return address and data channel ready right away, response depends on ack
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
@ -202,7 +206,7 @@ module up_axi (
up_wdata <= 'd0; up_wdata <= 'd0;
end else begin end else begin
if (up_axi_access == 1'b1) begin if (up_axi_access == 1'b1) begin
if (up_ack_s == 1'b1) begin if (up_axi_ack_s == 1'b1) begin
up_axi_access <= 1'b0; up_axi_access <= 1'b0;
end end
up_sel <= 1'b0; up_sel <= 1'b0;