diff --git a/projects/daq1/Makefile b/projects/daq1/Makefile deleted file mode 100644 index 4af18d6e7..000000000 --- a/projects/daq1/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -include ../scripts/project-toplevel.mk diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl deleted file mode 100644 index be86eb1f4..000000000 --- a/projects/daq1/common/daq1_bd.tcl +++ /dev/null @@ -1,143 +0,0 @@ - -# ad9122 interface - -create_bd_port -dir I dac_clk_in_p -create_bd_port -dir I dac_clk_in_n -create_bd_port -dir O dac_clk_out_p -create_bd_port -dir O dac_clk_out_n -create_bd_port -dir O dac_frame_out_p -create_bd_port -dir O dac_frame_out_n -create_bd_port -dir O -from 15 -to 0 dac_data_out_p -create_bd_port -dir O -from 15 -to 0 dac_data_out_n - -# ad9684 interface - -create_bd_port -dir I adc_clk_in_p -create_bd_port -dir I adc_clk_in_n -create_bd_port -dir I -from 13 -to 0 adc_data_in_p -create_bd_port -dir I -from 13 -to 0 adc_data_in_n - -# daq1 irq - -create_bd_port -dir I spi_int - -# dac peripherals - -ad_ip_instance axi_ad9122 axi_ad9122_core - -ad_ip_instance axi_dmac axi_ad9122_dma -ad_ip_parameter axi_ad9122_dma CONFIG.DMA_TYPE_SRC 0 -ad_ip_parameter axi_ad9122_dma CONFIG.DMA_TYPE_DEST 2 -ad_ip_parameter axi_ad9122_dma CONFIG.ID 0 -ad_ip_parameter axi_ad9122_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter axi_ad9122_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9122_dma CONFIG.DMA_LENGTH_WIDTH 24 -ad_ip_parameter axi_ad9122_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad9122_dma CONFIG.CYCLIC 1 -ad_ip_parameter axi_ad9122_dma CONFIG.DMA_DATA_WIDTH_DEST 128 - -ad_ip_instance util_upack util_upack_ad9122 -ad_ip_parameter util_upack_ad9122 CONFIG.CHANNEL_DATA_WIDTH 64 -ad_ip_parameter util_upack_ad9122 CONFIG.NUM_OF_CHANNELS 2 - -# adc peripherals - -ad_ip_instance axi_ad9684 axi_ad9684_core -ad_ip_parameter axi_ad9684_core CONFIG.OR_STATUS 0 - -ad_ip_instance axi_dmac axi_ad9684_dma -ad_ip_parameter axi_ad9684_dma CONFIG.DMA_TYPE_SRC 1 -ad_ip_parameter axi_ad9684_dma CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter axi_ad9684_dma CONFIG.ID 1 -ad_ip_parameter axi_ad9684_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter axi_ad9684_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9684_dma CONFIG.DMA_LENGTH_WIDTH 24 -ad_ip_parameter axi_ad9684_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad9684_dma CONFIG.FIFO_SIZE 16 -ad_ip_parameter axi_ad9684_dma CONFIG.CYCLIC 0 - -ad_ip_instance util_cpack util_cpack_ad9684 -ad_ip_parameter util_cpack_ad9684 CONFIG.CHANNEL_DATA_WIDTH 32 -ad_ip_parameter util_cpack_ad9684 CONFIG.NUM_OF_CHANNELS 2 - -# connections (dac) - -ad_connect dac_clk axi_ad9122_core/dac_div_clk -ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk -ad_connect dac_clk util_upack_ad9122/dac_clk - -ad_connect dac_clk_in_p axi_ad9122_core/dac_clk_in_p -ad_connect dac_clk_in_n axi_ad9122_core/dac_clk_in_n -ad_connect dac_clk_out_p axi_ad9122_core/dac_clk_out_p -ad_connect dac_clk_out_n axi_ad9122_core/dac_clk_out_n -ad_connect dac_frame_out_p axi_ad9122_core/dac_frame_out_p -ad_connect dac_frame_out_n axi_ad9122_core/dac_frame_out_n -ad_connect dac_data_out_p axi_ad9122_core/dac_data_out_p -ad_connect dac_data_out_n axi_ad9122_core/dac_data_out_n - -ad_connect axi_ad9122_core/dac_enable_0 util_upack_ad9122/dac_enable_0 -ad_connect axi_ad9122_core/dac_ddata_0 util_upack_ad9122/dac_data_0 -ad_connect axi_ad9122_core/dac_valid_0 util_upack_ad9122/dac_valid_0 -ad_connect axi_ad9122_core/dac_enable_1 util_upack_ad9122/dac_enable_1 -ad_connect axi_ad9122_core/dac_ddata_1 util_upack_ad9122/dac_data_1 -ad_connect axi_ad9122_core/dac_valid_1 util_upack_ad9122/dac_valid_1 -ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow - -ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en -ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout -ad_connect util_upack_ad9122/dac_sync axi_ad9122_core/dac_sync_in - -# connections (adc) - -ad_connect adc_clk axi_ad9684_core/adc_clk -ad_connect sys_200m_clk axi_ad9684_core/delay_clk -ad_connect sys_cpu_clk axi_ad9684_dma/s_axis_aclk -ad_connect adc_clk util_cpack_ad9684/adc_clk - -ad_connect adc_clk_in_p axi_ad9684_core/adc_clk_in_p -ad_connect adc_clk_in_n axi_ad9684_core/adc_clk_in_n -ad_connect axi_ad9684_core/adc_data_or_p GND -ad_connect axi_ad9684_core/adc_data_or_n GND -ad_connect adc_data_in_p axi_ad9684_core/adc_data_in_p -ad_connect adc_data_in_n axi_ad9684_core/adc_data_in_n - -ad_connect axi_ad9684_core/adc_rst util_cpack_ad9684/adc_rst -ad_connect axi_ad9684_core/adc_enable_0 util_cpack_ad9684/adc_enable_0 -ad_connect axi_ad9684_core/adc_valid_0 util_cpack_ad9684/adc_valid_0 -ad_connect axi_ad9684_core/adc_data_0 util_cpack_ad9684/adc_data_0 -ad_connect axi_ad9684_core/adc_enable_1 util_cpack_ad9684/adc_enable_1 -ad_connect axi_ad9684_core/adc_valid_1 util_cpack_ad9684/adc_valid_1 -ad_connect axi_ad9684_core/adc_data_1 util_cpack_ad9684/adc_data_1 -ad_connect axi_ad9684_core/adc_dovf axi_ad9684_fifo/adc_wovf - -ad_connect adc_clk axi_ad9684_fifo/adc_clk -ad_connect sys_cpu_clk axi_ad9684_fifo/dma_clk -ad_connect axi_ad9684_core/adc_rst axi_ad9684_fifo/adc_rst -ad_connect util_cpack_ad9684/adc_valid axi_ad9684_fifo/adc_wr -ad_connect util_cpack_ad9684/adc_data axi_ad9684_fifo/adc_wdata -ad_connect axi_ad9684_fifo/dma_wr axi_ad9684_dma/s_axis_valid -ad_connect axi_ad9684_fifo/dma_wdata axi_ad9684_dma/s_axis_data -ad_connect axi_ad9684_fifo/dma_wready axi_ad9684_dma/s_axis_ready -ad_connect axi_ad9684_fifo/dma_xfer_req axi_ad9684_dma/s_axis_xfer_req - - -# memory interconnect - -ad_cpu_interconnect 0x44A00000 axi_ad9122_core -ad_cpu_interconnect 0x44A20000 axi_ad9684_core -ad_cpu_interconnect 0x44A40000 axi_ad9122_dma -ad_cpu_interconnect 0x44A60000 axi_ad9684_dma -ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_200m_clk axi_ad9684_dma/m_dest_axi -ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi - -ad_connect sys_cpu_resetn axi_ad9684_dma/m_dest_axi_aresetn -ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn - -# interrupts - -ad_cpu_interrupt ps-11 mb-11 spi_int -ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq -ad_cpu_interrupt ps-13 mb-13 axi_ad9684_dma/irq - diff --git a/projects/daq1/common/daq1_qsys.tcl b/projects/daq1/common/daq1_qsys.tcl deleted file mode 100644 index bdf5f4ebf..000000000 --- a/projects/daq1/common/daq1_qsys.tcl +++ /dev/null @@ -1,123 +0,0 @@ - -# DAQ1 - -# DAC core - -add_instance axi_ad9122 axi_ad9122 -set_instance_parameter_value axi_ad9122 {ID} {0} -add_connection sys_clk.clk_reset axi_ad9122.s_axi_reset -add_connection sys_clk.clk axi_ad9122.s_axi_clock -add_interface axi_ad9122_device_if conduit end -set_interface_property axi_ad9122_device_if EXPORT_OF axi_ad9122.device_if - -# DAC unpack - -add_instance util_ad9122_upack util_upack -set_instance_parameter_value util_ad9122_upack {NUM_OF_CHANNELS} {2} -set_instance_parameter_value util_ad9122_upack {CHANNEL_DATA_WIDTH} {64} -add_connection axi_ad9122.if_dac_div_clk util_ad9122_upack.if_dac_clk -add_connection util_ad9122_upack.dac_ch_0 axi_ad9122.dac_ch_0 -add_connection util_ad9122_upack.dac_ch_1 axi_ad9122.dac_ch_1 - -# DAC DMA - -add_instance axi_ad9122_dma axi_dmac -set_instance_parameter_value axi_ad9122_dma {DMA_DATA_WIDTH_DEST} {128} -set_instance_parameter_value axi_ad9122_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_DEST} {2} -set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_SRC} {0} -set_instance_parameter_value axi_ad9122_dma {CYCLIC} {1} -set_instance_parameter_value axi_ad9122_dma {SYNC_TRANSFER_START} {0} -set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_SRC} {0} -set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_DEST} {0} -set_instance_parameter_value axi_ad9122_dma {DMA_LENGTH_WIDTH} {24} -add_connection sys_clk.clk_reset axi_ad9122_dma.s_axi_reset -add_connection sys_clk.clk axi_ad9122_dma.s_axi_clock -add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9122_dma.m_src_axi_reset -add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9122_dma.m_src_axi_clock -add_connection axi_ad9122.if_dac_div_clk axi_ad9122_dma.if_fifo_rd_clk -add_connection util_ad9122_upack.if_dac_valid axi_ad9122_dma.if_fifo_rd_en -add_connection axi_ad9122_dma.if_fifo_rd_dout util_ad9122_upack.if_dac_data -add_connection axi_ad9122_dma.if_fifo_rd_underflow axi_ad9122.if_dac_dunf - -# ADC core - -add_instance axi_ad9684 axi_ad9684 -set_instance_parameter_value axi_ad9684 {OR_STATUS} {0} -add_connection sys_clk.clk_reset axi_ad9684.s_axi_reset -add_connection sys_clk.clk axi_ad9684.s_axi_clock -add_interface axi_ad9684_device_if conduit end -set_interface_property axi_ad9684_device_if EXPORT_OF axi_ad9684.device_if - -# ADC pack - -add_instance util_ad9684_cpack util_cpack -set_instance_parameter_value util_ad9684_cpack {NUM_OF_CHANNELS} {2} -set_instance_parameter_value util_ad9684_cpack {CHANNEL_DATA_WIDTH} {32} -add_connection sys_clk.clk_reset util_ad9684_cpack.if_adc_rst -add_connection axi_ad9684.if_adc_clk util_ad9684_cpack.if_adc_clk -add_connection axi_ad9684.adc_ch_0 util_ad9684_cpack.adc_ch_0 -add_connection axi_ad9684.adc_ch_1 util_ad9684_cpack.adc_ch_1 - -# ADC FIFO - -add_instance ad9684_adcfifo util_adcfifo -set_instance_parameter_value ad9684_adcfifo {ADC_DATA_WIDTH} {64} -set_instance_parameter_value ad9684_adcfifo {DMA_DATA_WIDTH} {64} -set_instance_parameter_value ad9684_adcfifo {DMA_ADDRESS_WIDTH} {16} -add_connection sys_clk.clk_reset ad9684_adcfifo.if_adc_rst -add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9684_adcfifo.if_adc_rst -add_connection axi_ad9684.if_adc_clk ad9684_adcfifo.if_adc_clk -add_connection util_ad9684_cpack.if_adc_valid ad9684_adcfifo.if_adc_wr -add_connection util_ad9684_cpack.if_adc_data ad9684_adcfifo.if_adc_wdata -add_connection sys_ddr3_cntrl.emif_usr_clk ad9684_adcfifo.if_dma_clk - -# ADC DMA - -add_instance axi_ad9684_dma axi_dmac -set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_SRC} {1} -set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_DEST} {0} -set_instance_parameter_value axi_ad9684_dma {ID} {1} -set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_SRC} {0} -set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_DEST} {0} -set_instance_parameter_value axi_ad9684_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_ad9684_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_ad9684_dma {FIFO_SIZE} {16} -set_instance_parameter_value axi_ad9684_dma {CYCLIC} {0} -add_connection sys_clk.clk_reset axi_ad9684_dma.s_axi_reset -add_connection sys_clk.clk axi_ad9684_dma.s_axi_clock -add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9684_dma.m_dest_axi_reset -add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.m_dest_axi_clock -add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.if_s_axis_aclk -add_connection ad9684_adcfifo.if_dma_wr axi_ad9684_dma.if_s_axis_valid -add_connection ad9684_adcfifo.if_dma_wdata axi_ad9684_dma.if_s_axis_data -add_connection axi_ad9684_dma.if_s_axis_ready ad9684_adcfifo.if_dma_wready -add_connection axi_ad9684_dma.if_s_axis_xfer_req ad9684_adcfifo.if_dma_xfer_req - -# IRQ bridge for the CPLD IRQ signal - -add_instance irq_bridge altera_irq_bridge -set_instance_parameter_value irq_bridge {IRQ_WIDTH} {1} -add_connection sys_clk.clk_reset irq_bridge.clk_reset -add_connection sys_clk.clk irq_bridge.clk -add_interface spi_int conduit end -set_interface_property spi_int EXPORT_OF irq_bridge.receiver_irq - -# cpu interconnects - -ad_cpu_interconnect 0x44A00000 axi_ad9122.s_axi -ad_cpu_interconnect 0x44A20000 axi_ad9684.s_axi -ad_cpu_interconnect 0x44A40000 axi_ad9122_dma.s_axi -ad_cpu_interconnect 0x44A60000 axi_ad9684_dma.s_axi - -# dma interconnects - -ad_dma_interconnect axi_ad9684_dma.m_dest_axi -ad_dma_interconnect axi_ad9122_dma.m_src_axi - -# interrupts - -ad_cpu_interrupt 9 irq_bridge.sender0_irq -ad_cpu_interrupt 10 axi_ad9684_dma.interrupt_sender -ad_cpu_interrupt 11 axi_ad9122_dma.interrupt_sender - diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v deleted file mode 100644 index 9adf636d0..000000000 --- a/projects/daq1/common/daq1_spi.v +++ /dev/null @@ -1,106 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module daq1_spi ( - - input spi_csn, - input spi_clk, - input spi_mosi, - output spi_miso, - - inout spi_sdio); - - // device address - - localparam [ 7:0] SPI_SEL_AD9684 = 8'h80; - localparam [ 7:0] SPI_SEL_AD9122 = 8'h81; - localparam [ 7:0] SPI_SEL_AD9523 = 8'h82; - localparam [ 7:0] SPI_SEL_CPLD = 8'h83; - - // internal registers - - reg [ 5:0] spi_count = 6'b0; - reg spi_rd_wr_n = 1'b0; - reg spi_enable = 1'b0; - reg [ 7:0] spi_device_addr = 8'b0; - - // internal signals - - wire spi_enable_s; - - // check on rising edge and change on falling edge - - assign spi_enable_s = spi_enable & ~spi_csn; - - always @(posedge spi_clk or posedge spi_csn) begin - if (spi_csn == 1'b1) begin - spi_count <= 6'b0000000; - spi_rd_wr_n <= 1'b0; - spi_device_addr <= 8'b00000000; - end else begin - spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; - if (spi_count <= 6'd7) begin - spi_device_addr <= {spi_device_addr[6:0], spi_mosi}; - end - if (spi_count == 6'd8) begin - spi_rd_wr_n <= spi_mosi; - end - end - end - - always @(negedge spi_clk or posedge spi_csn) begin - if (spi_csn == 1'b1) begin - spi_enable <= 1'b0; - end else begin - if (((spi_device_addr == SPI_SEL_AD9684) && (spi_count == 6'd24)) || - ((spi_device_addr == SPI_SEL_AD9122) && (spi_count == 6'd16)) || - ((spi_device_addr == SPI_SEL_AD9523) && (spi_count == 6'd24)) || - ((spi_device_addr == SPI_SEL_CPLD) && (spi_count == 6'd16))) begin - spi_enable <= spi_rd_wr_n; - end - end - end - - // io logic - - assign spi_miso = spi_sdio; - assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/daq1/cpld/daq1_cpld.ucf b/projects/daq1/cpld/daq1_cpld.ucf deleted file mode 100644 index 67a31e5d4..000000000 --- a/projects/daq1/cpld/daq1_cpld.ucf +++ /dev/null @@ -1,30 +0,0 @@ -#PACE: Start of Constraints generated by PACE - -#PACE: Start of PACE I/O Pin Assignments -NET "adc_fda" LOC = "P6" | IOSTANDARD = LVCMOS33 ; -NET "adc_fdb" LOC = "P7" | IOSTANDARD = LVCMOS33 ; -NET "adc_pwdn_stby" LOC = "P10" | IOSTANDARD = LVCMOS33 ; -NET "adc_spicsn" LOC = "P13" | IOSTANDARD = LVCMOS33 ; -NET "adc_status_n" LOC = "P9" | IOSTANDARD = LVCMOS33 ; -NET "adc_status_p" LOC = "P8" | IOSTANDARD = LVCMOS33 ; -NET "clk_pwdnn" LOC = "P20" | IOSTANDARD = LVCMOS33 ; -NET "clk_resetn" LOC = "P25" | IOSTANDARD = LVCMOS33 ; -NET "clk_spicsn" LOC = "P15" | IOSTANDARD = LVCMOS33 ; -NET "clk_status1" LOC = "P17" | IOSTANDARD = LVCMOS33 ; -NET "clk_status2" LOC = "P18" | IOSTANDARD = LVCMOS33 ; -NET "clk_syncn" LOC = "P24" | IOSTANDARD = LVCMOS33 ; -NET "dac_irqn" LOC = "P26" | IOSTANDARD = LVCMOS33 ; -NET "dac_resetn" LOC = "P27" | IOSTANDARD = LVCMOS33 ; -NET "dac_spicsn" LOC = "P14" | IOSTANDARD = LVCMOS33 ; -NET "fmc_irq" LOC = "P2" | IOSTANDARD = LVCMOS25; -NET "fmc_spi_csn" LOC = "P5" | IOSTANDARD = LVCMOS25 ; -NET "fmc_spi_sclk" LOC = "P4" | IOSTANDARD = LVCMOS25 ; -NET "fmc_spi_sdio" LOC = "P1" | IOSTANDARD = LVCMOS25 ; -NET "sclk" LOC = "P30" | IOSTANDARD = LVCMOS33 ; -NET "sdio" LOC = "P28" | IOSTANDARD = LVCMOS33 ; - -#PACE: Start of PACE Area Constraints - -#PACE: Start of PACE Prohibit Constraints - -#PACE: End of Constraints generated by PACE diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v deleted file mode 100644 index 61181fd41..000000000 --- a/projects/daq1/cpld/daq1_cpld.v +++ /dev/null @@ -1,258 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module daq1_cpld ( - - // FMC SPI interface - - input fmc_spi_sclk, - input fmc_spi_csn, - inout fmc_spi_sdio, - output fmc_irq, - - // on board SPI interface - - output adc_spicsn, - output dac_spicsn, - output clk_spicsn, - output sclk, - inout sdio, - - // control and status lines - - input adc_fda, - input adc_fdb, - input adc_status_p, - input adc_status_n, - output adc_pwdn_stby, - - input dac_irqn, - output dac_resetn, - - input clk_status1, - input clk_status2, - output clk_pwdnn, - output clk_syncn, - output clk_resetn -); - - // FMC SPI Selects - - localparam [ 7:0] FMC_SPI_SEL_AD9684 = 8'h80; - localparam [ 7:0] FMC_SPI_SEL_AD9122 = 8'h81; - localparam [ 7:0] FMC_SPI_SEL_AD9523 = 8'h82; - localparam [ 7:0] FMC_SPI_SEL_CPLD = 8'h83; - - // CPLD Register Map Addresses - - localparam [ 6:0] CPLD_VERSION_ADDR = 7'h00; - localparam [ 6:0] ADC_CONTROL_ADDR = 7'h10; - localparam [ 6:0] DAC_CONTROL_ADDR = 7'h11; - localparam [ 6:0] CLK_CONTROL_ADDR = 7'h12; - localparam [ 6:0] IRQ_MASK_ADDR = 7'h13; - localparam [ 6:0] ADC_STATUS_ADDR = 7'h20; - localparam [ 6:0] DAC_STATUS_ADDR = 7'h21; - localparam [ 6:0] CLK_STATUS_ADDR = 7'h22; - - localparam [ 7:0] CPLD_VERSION = 8'h11; - - // Internal Registers/Signals - - reg [ 7:0] fmc_spi_dev_sel = 8'b0; - reg [ 7:0] fmc_cpld_addr = 8'b0; - reg [ 5:0] fmc_spi_counter = 6'b0; - reg fmc_spi_csn_enb = 1'b1; - - reg [ 7:0] adc_control = 8'b0; - reg [ 7:0] dac_control = 8'b0; - reg [ 7:0] clk_control = 8'b0; - - reg [ 7:0] adc_status = 8'b0; - reg [ 7:0] dac_status = 8'b0; - reg [ 7:0] clk_status = 8'b0; - - reg cpld_to_fpga = 1'b0; - reg [ 7:0] cpld_rdata = 8'b0; - reg cpld_rdata_bit = 1'b0; - reg [ 2:0] cpld_rdata_index = 3'h0; - reg [ 7:0] cpld_wdata = 8'b0; - reg [ 7:0] cpld_irq_mask = 8'b0; - reg [ 7:0] cpld_irq = 8'b0; - - wire rdnwr; - wire cpld_rdata_s; - - // SCLK counter for control signals - - always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin - if (fmc_spi_csn == 1'b1) begin - fmc_spi_dev_sel <= 8'h0; - fmc_cpld_addr <= 8'h0; - end else begin - if (fmc_spi_counter <= 7) begin - fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio}; - end - if (fmc_spi_counter <= 15) begin - fmc_cpld_addr <= {fmc_cpld_addr[6:0], fmc_spi_sdio}; - end - end - end - - // chip select control - - assign adc_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9684) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; - assign dac_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9122) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; - assign clk_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9523) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; - assign cpld_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_CPLD) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; - - // SPI control and data - - assign sdio = cpld_to_fpga ? 1'bZ : fmc_spi_sdio; - assign fmc_spi_sdio = cpld_to_fpga ? cpld_rdata_s : 1'bZ ; - assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit; - assign rdnwr = fmc_cpld_addr[7]; - - assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0; - - always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin - if (fmc_spi_csn == 1'b1) begin - fmc_spi_counter <= 6'h0; - cpld_to_fpga <= 1'b0; - fmc_spi_csn_enb <= 1'b1; - end else begin - fmc_spi_counter <= (fmc_spi_counter <= 6'h3F) ? fmc_spi_counter + 1 : fmc_spi_counter; - fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0; - if (adc_spicsn & clk_spicsn) begin - cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0; - end else begin - cpld_to_fpga <= (fmc_spi_counter >= 23) ? rdnwr : 1'b0; - end - end - end - - // Internal register read access - - always @(fmc_cpld_addr) begin - case (fmc_cpld_addr[6:0]) - CPLD_VERSION_ADDR : - cpld_rdata <= CPLD_VERSION; - ADC_CONTROL_ADDR : - cpld_rdata <= adc_pwdn_stby; - DAC_CONTROL_ADDR : - cpld_rdata <= dac_resetn; - CLK_CONTROL_ADDR : - cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn}; - IRQ_MASK_ADDR: - cpld_rdata <= cpld_irq_mask; - ADC_STATUS_ADDR : - cpld_rdata <= {adc_status_p, adc_fdb, adc_fda}; - DAC_STATUS_ADDR : - cpld_rdata <= dac_irqn; - CLK_STATUS_ADDR : - cpld_rdata <= {clk_status2, clk_status1}; - default: - cpld_rdata <= 8'hFA; - endcase - end - - always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin - if (fmc_spi_csn == 1'b1) begin - cpld_rdata_bit <= cpld_rdata[7]; - cpld_rdata_index <= 3'h6; - end else begin - if (cpld_to_fpga == 1'b1) begin - cpld_rdata_bit <= cpld_rdata[cpld_rdata_index]; - cpld_rdata_index <= cpld_rdata_index - 1; - end - end - end - - // Internal register write access - - always @(cpld_to_fpga, cpld_spicsn, fmc_spi_counter) begin - if ((cpld_to_fpga == 1'b0) && - (cpld_spicsn == 1'b0) && - (fmc_spi_counter == 8'h18)) begin - case (fmc_cpld_addr[6:0]) - ADC_CONTROL_ADDR : - adc_control <= cpld_wdata; - DAC_CONTROL_ADDR : - dac_control <= cpld_wdata; - CLK_CONTROL_ADDR : - clk_control <= cpld_wdata; - IRQ_MASK_ADDR: - cpld_irq_mask <= cpld_wdata; - endcase - end - end - - always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin - if (fmc_spi_csn == 1'b1) begin - cpld_wdata <= 8'h0; - end else begin - if (fmc_spi_counter >= 16) begin - cpld_wdata <= {cpld_wdata[6:0], fmc_spi_sdio}; - end - end - end - - // input/output logic - - // AD9648 - - assign adc_pwdn_stby = adc_control[0]; - - // AD9122 - - assign dac_resetn = dac_control[0]; - - // AD9523-1 - - assign clk_pwdnn = clk_control[0]; - assign clk_resetn = clk_control[1]; - assign clk_syncn = clk_control[2]; - - // interrupt logic - - always @(*) begin - cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda}; - end - - assign fmc_irq = |(~cpld_irq_mask & cpld_irq); - -endmodule - diff --git a/projects/daq1/cpld/daq1_cpld.xise b/projects/daq1/cpld/daq1_cpld.xise deleted file mode 100644 index 883441fe6..000000000 --- a/projects/daq1/cpld/daq1_cpld.xise +++ /dev/null @@ -1,241 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile deleted file mode 100644 index 8451ecd0c..000000000 --- a/projects/daq1/zc706/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := daq1_zc706 - -M_DEPS += ../common/daq1_spi.v -M_DEPS += ../common/daq1_bd.tcl -M_DEPS += ../../common/zc706/zc706_system_constr.xdc -M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc -M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_ad9122 -LIB_DEPS += axi_ad9684 -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_spdif_tx -LIB_DEPS += util_cpack -LIB_DEPS += util_upack -LIB_DEPS += xilinx/axi_adcfifo - -include ../../scripts/project-xilinx.mk diff --git a/projects/daq1/zc706/system_bd.tcl b/projects/daq1/zc706/system_bd.tcl deleted file mode 100644 index 40db91795..000000000 --- a/projects/daq1/zc706/system_bd.tcl +++ /dev/null @@ -1,10 +0,0 @@ - -set adc_fifo_name axi_ad9684_fifo -set adc_fifo_address_width 18 -set adc_data_width 64 -set adc_dma_data_width 64 - -source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl -source ../common/daq1_bd.tcl - diff --git a/projects/daq1/zc706/system_constr.xdc b/projects/daq1/zc706/system_constr.xdc deleted file mode 100644 index 6cdaa0e7f..000000000 --- a/projects/daq1/zc706/system_constr.xdc +++ /dev/null @@ -1,83 +0,0 @@ - -# daq1 - -set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## G02 FMC_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## G03 FMC_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p] ; ## H37 FMC_LPC_LA32_P -set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n] ; ## H38 FMC_LPC_LA32_N -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]] ; ## H20 FMC_LPC_LA15_N -set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]] ; ## G21 FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]] ; ## D20 FMC_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]] ; ## D21 FMC_LPC_LA17_CC_N -set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]] ; ## G25 FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]] ; ## C22 FMC_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]] ; ## C23 FMC_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]] ; ## H28 FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]] ; ## H29 FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]] ; ## C27 FMC_LPC_LA27_N -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]] ; ## G30 FMC_LPC_LA29_P -set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]] ; ## G31 FMC_LPC_LA29_N -set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]] ; ## H32 FMC_LPC_LA28_N -set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]] ; ## G33 FMC_LPC_LA31_P -set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]] ; ## G34 FMC_LPC_LA31_N -set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]] ; ## H34 FMC_LPC_LA30_P -set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]] ; ## H35 FMC_LPC_LA30_N -set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]] ; ## G36 FMC_LPC_LA33_P -set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]] ; ## G37 FMC_LPC_LA33_N - -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## G09 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## H08 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## D08 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## D09 FMC_LPC_LA01_CC_N - -set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## H05 FMC_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H04 FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports spi_int] ; ## G19 FMC_LPC_LA16_N - -# clocks - -create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 2.00 [get_ports adc_clk_in_p] - diff --git a/projects/daq1/zc706/system_project.tcl b/projects/daq1/zc706/system_project.tcl deleted file mode 100644 index 619e69706..000000000 --- a/projects/daq1/zc706/system_project.tcl +++ /dev/null @@ -1,16 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx daq1_zc706 -adi_project_files daq1_zc706 [list \ - "../common/daq1_spi.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ - "system_top.v" ] - -adi_project_run daq1_zc706 - diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v deleted file mode 100644 index bc6e12119..000000000 --- a/projects/daq1/zc706/system_top.v +++ /dev/null @@ -1,235 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [14:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [23:0] hdmi_data, - - output spdif, - - inout iic_scl, - inout iic_sda, - - input dac_clk_in_p, - input dac_clk_in_n, - output dac_clk_out_p, - output dac_clk_out_n, - output dac_frame_out_p, - output dac_frame_out_n, - output [15:0] dac_data_out_p, - output [15:0] dac_data_out_n, - - input adc_clk_in_p, - input adc_clk_in_n, - input [13:0] adc_data_in_p, - input [13:0] adc_data_in_n, - - output spi_clk, - output spi_csn, - inout spi_sdio, - input spi_int, - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output [ 0:0] ddr3_ck_n, - output [ 0:0] ddr3_ck_p, - output [ 0:0] ddr3_cke, - output [ 0:0] ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output [ 0:0] ddr3_odt, - output ddr3_ras_n, - output ddr3_reset_n, - output ddr3_we_n); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire spi_mosi; - wire spi_miso; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd ( - .dio_t (gpio_t[14:0]), - .dio_i (gpio_o[14:0]), - .dio_o (gpio_i[14:0]), - .dio_p (gpio_bd)); - - daq1_spi i_spi ( - .spi_csn (spi_csn), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); - - system_wrapper i_system_wrapper ( - .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .spdif (spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o (), - .spi_int (spi_int)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/daq1/zed/Makefile b/projects/daq1/zed/Makefile deleted file mode 100644 index 78c4f5585..000000000 --- a/projects/daq1/zed/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := daq1_zed - -M_DEPS += ../common/daq1_spi.v -M_DEPS += ../common/daq1_bd.tcl -M_DEPS += ../../common/zed/zed_system_constr.xdc -M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../common/xilinx/adcfifo_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_ad9122 -LIB_DEPS += axi_ad9684 -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_i2s_adi -LIB_DEPS += axi_spdif_tx -LIB_DEPS += util_adcfifo -LIB_DEPS += util_cpack -LIB_DEPS += util_i2c_mixer -LIB_DEPS += util_upack - -include ../../scripts/project-xilinx.mk diff --git a/projects/daq1/zed/system_bd.tcl b/projects/daq1/zed/system_bd.tcl deleted file mode 100644 index e3c2f0953..000000000 --- a/projects/daq1/zed/system_bd.tcl +++ /dev/null @@ -1,9 +0,0 @@ - -set adc_fifo_name axi_ad9684_fifo -set adc_fifo_address_width 10 -set adc_data_width 64 -set adc_dma_data_width 64 - -source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl -source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl -source ../common/daq1_bd.tcl diff --git a/projects/daq1/zed/system_constr.xdc b/projects/daq1/zed/system_constr.xdc deleted file mode 100644 index 15ccb9380..000000000 --- a/projects/daq1/zed/system_constr.xdc +++ /dev/null @@ -1,83 +0,0 @@ - -# daq1 - -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## G02 FMC_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## G03 FMC_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p] ; ## H37 FMC_LPC_LA32_P -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n] ; ## H38 FMC_LPC_LA32_N -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]] ; ## H20 FMC_LPC_LA15_N -set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]] ; ## G21 FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]] ; ## D20 FMC_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]] ; ## D21 FMC_LPC_LA17_CC_N -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]] ; ## G25 FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]] ; ## C22 FMC_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]] ; ## C23 FMC_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]] ; ## A18 FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]] ; ## H29 FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]] ; ## C27 FMC_LPC_LA27_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]] ; ## G30 FMC_LPC_LA29_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]] ; ## G31 FMC_LPC_LA29_N -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]] ; ## H32 FMC_LPC_LA28_N -set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]] ; ## G33 FMC_LPC_LA31_P -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]] ; ## G34 FMC_LPC_LA31_N -set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]] ; ## H34 FMC_LPC_LA30_P -set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]] ; ## H35 FMC_LPC_LA30_N -set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]] ; ## G36 FMC_LPC_LA33_P -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]] ; ## G37 FMC_LPC_LA33_N - -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## G09 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## H08 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## D08 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## D09 FMC_LPC_LA01_CC_N - -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H04 FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## H05 FMC_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports spi_int] ; ## G19 FMC_LPC_LA16_N - -# clocks - -create_clock -name dac_clk_in -period 2.222 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 2.222 [get_ports adc_clk_in_p] - diff --git a/projects/daq1/zed/system_project.tcl b/projects/daq1/zed/system_project.tcl deleted file mode 100644 index 42fddf8a9..000000000 --- a/projects/daq1/zed/system_project.tcl +++ /dev/null @@ -1,15 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx daq1_zed -adi_project_files daq1_zed [list \ - "../common/daq1_spi.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "system_top.v" ] - -adi_project_run daq1_zed - diff --git a/projects/daq1/zed/system_top.v b/projects/daq1/zed/system_top.v deleted file mode 100644 index ca8348d7b..000000000 --- a/projects/daq1/zed/system_top.v +++ /dev/null @@ -1,236 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [31:0] gpio_bd, - - output i2s_mclk, - output i2s_bclk, - output i2s_lrclk, - output i2s_sdata_out, - input i2s_sdata_in, - - inout iic_scl, - inout iic_sda, - inout [ 1:0] iic_mux_scl, - inout [ 1:0] iic_mux_sda, - - input otg_vbusoc, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [15:0] hdmi_data, - - output spdif, - - input dac_clk_in_p, - input dac_clk_in_n, - output dac_clk_out_p, - output dac_clk_out_n, - output dac_frame_out_p, - output dac_frame_out_n, - output [15:0] dac_data_out_p, - output [15:0] dac_data_out_n, - - input adc_clk_in_p, - input adc_clk_in_n, - input [13:0] adc_data_in_p, - input [13:0] adc_data_in_n, - - output spi_clk, - output spi_csn, - inout spi_sdio, - input spi_int); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire spi_mosi; - wire spi_miso; - wire [ 1:0] iic_mux_scl_o_s; - wire iic_mux_scl_t_s; - wire [ 1:0] iic_mux_sda_i_s; - wire [ 1:0] iic_mux_sda_o_s; - wire iic_mux_sda_t_s; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(32)) i_gpio_bd ( - .dio_t (gpio_t[31:0]), - .dio_i (gpio_o[31:0]), - .dio_o (gpio_i[31:0]), - .dio_p (gpio_bd)); - - daq1_spi i_spi ( - .spi_csn (spi_csn), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); - - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl ( - .dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}), - .dio_i (iic_mux_scl_o_s), - .dio_o (iic_mux_scl_i_s), - .dio_p (iic_mux_scl)); - - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda ( - .dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}), - .dio_i (iic_mux_sda_o_s), - .dio_o (iic_mux_sda_i_s), - .dio_p (iic_mux_sda)); - - system_wrapper i_system_wrapper ( - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_fmc_scl_io (iic_scl), - .iic_fmc_sda_io (iic_sda), - .iic_mux_scl_i (iic_mux_scl_i_s), - .iic_mux_scl_o (iic_mux_scl_o_s), - .iic_mux_scl_t (iic_mux_scl_t_s), - .iic_mux_sda_i (iic_mux_sda_i_s), - .iic_mux_sda_o (iic_mux_sda_o_s), - .iic_mux_sda_t (iic_mux_sda_t_s), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .otg_vbusoc (otg_vbusoc), - .spdif (spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o (), - .spi_int (spi_int)); - -endmodule - -// *************************************************************************** -// ***************************************************************************