daq1: Move project to a feature branch
Istvan Csomortani
István Csomortáni
parent
1c959a8f85
commit
18bdf91254
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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@ -1,143 +0,0 @@
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# ad9122 interface
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create_bd_port -dir I dac_clk_in_p
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create_bd_port -dir I dac_clk_in_n
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create_bd_port -dir O dac_clk_out_p
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create_bd_port -dir O dac_clk_out_n
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create_bd_port -dir O dac_frame_out_p
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create_bd_port -dir O dac_frame_out_n
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create_bd_port -dir O -from 15 -to 0 dac_data_out_p
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create_bd_port -dir O -from 15 -to 0 dac_data_out_n
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# ad9684 interface
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create_bd_port -dir I adc_clk_in_p
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create_bd_port -dir I adc_clk_in_n
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create_bd_port -dir I -from 13 -to 0 adc_data_in_p
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create_bd_port -dir I -from 13 -to 0 adc_data_in_n
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# daq1 irq
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create_bd_port -dir I spi_int
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# dac peripherals
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ad_ip_instance axi_ad9122 axi_ad9122_core
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ad_ip_instance axi_dmac axi_ad9122_dma
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ad_ip_parameter axi_ad9122_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad9122_dma CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter axi_ad9122_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9122_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9122_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9122_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9122_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9122_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_ad9122_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance util_upack util_upack_ad9122
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ad_ip_parameter util_upack_ad9122 CONFIG.CHANNEL_DATA_WIDTH 64
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ad_ip_parameter util_upack_ad9122 CONFIG.NUM_OF_CHANNELS 2
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# adc peripherals
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ad_ip_instance axi_ad9684 axi_ad9684_core
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ad_ip_parameter axi_ad9684_core CONFIG.OR_STATUS 0
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ad_ip_instance axi_dmac axi_ad9684_dma
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ad_ip_parameter axi_ad9684_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9684_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9684_dma CONFIG.ID 1
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ad_ip_parameter axi_ad9684_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9684_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9684_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9684_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9684_dma CONFIG.FIFO_SIZE 16
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ad_ip_parameter axi_ad9684_dma CONFIG.CYCLIC 0
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ad_ip_instance util_cpack util_cpack_ad9684
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ad_ip_parameter util_cpack_ad9684 CONFIG.CHANNEL_DATA_WIDTH 32
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ad_ip_parameter util_cpack_ad9684 CONFIG.NUM_OF_CHANNELS 2
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# connections (dac)
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ad_connect dac_clk axi_ad9122_core/dac_div_clk
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ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
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ad_connect dac_clk util_upack_ad9122/dac_clk
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ad_connect dac_clk_in_p axi_ad9122_core/dac_clk_in_p
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ad_connect dac_clk_in_n axi_ad9122_core/dac_clk_in_n
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ad_connect dac_clk_out_p axi_ad9122_core/dac_clk_out_p
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ad_connect dac_clk_out_n axi_ad9122_core/dac_clk_out_n
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ad_connect dac_frame_out_p axi_ad9122_core/dac_frame_out_p
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ad_connect dac_frame_out_n axi_ad9122_core/dac_frame_out_n
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ad_connect dac_data_out_p axi_ad9122_core/dac_data_out_p
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ad_connect dac_data_out_n axi_ad9122_core/dac_data_out_n
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ad_connect axi_ad9122_core/dac_enable_0 util_upack_ad9122/dac_enable_0
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ad_connect axi_ad9122_core/dac_ddata_0 util_upack_ad9122/dac_data_0
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ad_connect axi_ad9122_core/dac_valid_0 util_upack_ad9122/dac_valid_0
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ad_connect axi_ad9122_core/dac_enable_1 util_upack_ad9122/dac_enable_1
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ad_connect axi_ad9122_core/dac_ddata_1 util_upack_ad9122/dac_data_1
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ad_connect axi_ad9122_core/dac_valid_1 util_upack_ad9122/dac_valid_1
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ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow
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ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en
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ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout
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ad_connect util_upack_ad9122/dac_sync axi_ad9122_core/dac_sync_in
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# connections (adc)
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ad_connect adc_clk axi_ad9684_core/adc_clk
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ad_connect sys_200m_clk axi_ad9684_core/delay_clk
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ad_connect sys_cpu_clk axi_ad9684_dma/s_axis_aclk
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ad_connect adc_clk util_cpack_ad9684/adc_clk
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ad_connect adc_clk_in_p axi_ad9684_core/adc_clk_in_p
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ad_connect adc_clk_in_n axi_ad9684_core/adc_clk_in_n
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ad_connect axi_ad9684_core/adc_data_or_p GND
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ad_connect axi_ad9684_core/adc_data_or_n GND
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ad_connect adc_data_in_p axi_ad9684_core/adc_data_in_p
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ad_connect adc_data_in_n axi_ad9684_core/adc_data_in_n
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ad_connect axi_ad9684_core/adc_rst util_cpack_ad9684/adc_rst
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ad_connect axi_ad9684_core/adc_enable_0 util_cpack_ad9684/adc_enable_0
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ad_connect axi_ad9684_core/adc_valid_0 util_cpack_ad9684/adc_valid_0
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ad_connect axi_ad9684_core/adc_data_0 util_cpack_ad9684/adc_data_0
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ad_connect axi_ad9684_core/adc_enable_1 util_cpack_ad9684/adc_enable_1
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ad_connect axi_ad9684_core/adc_valid_1 util_cpack_ad9684/adc_valid_1
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ad_connect axi_ad9684_core/adc_data_1 util_cpack_ad9684/adc_data_1
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ad_connect axi_ad9684_core/adc_dovf axi_ad9684_fifo/adc_wovf
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ad_connect adc_clk axi_ad9684_fifo/adc_clk
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ad_connect sys_cpu_clk axi_ad9684_fifo/dma_clk
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ad_connect axi_ad9684_core/adc_rst axi_ad9684_fifo/adc_rst
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ad_connect util_cpack_ad9684/adc_valid axi_ad9684_fifo/adc_wr
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ad_connect util_cpack_ad9684/adc_data axi_ad9684_fifo/adc_wdata
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ad_connect axi_ad9684_fifo/dma_wr axi_ad9684_dma/s_axis_valid
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ad_connect axi_ad9684_fifo/dma_wdata axi_ad9684_dma/s_axis_data
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ad_connect axi_ad9684_fifo/dma_wready axi_ad9684_dma/s_axis_ready
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ad_connect axi_ad9684_fifo/dma_xfer_req axi_ad9684_dma/s_axis_xfer_req
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# memory interconnect
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ad_cpu_interconnect 0x44A00000 axi_ad9122_core
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ad_cpu_interconnect 0x44A20000 axi_ad9684_core
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ad_cpu_interconnect 0x44A40000 axi_ad9122_dma
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ad_cpu_interconnect 0x44A60000 axi_ad9684_dma
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ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_200m_clk axi_ad9684_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
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ad_connect sys_cpu_resetn axi_ad9684_dma/m_dest_axi_aresetn
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ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-11 mb-11 spi_int
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ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq
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ad_cpu_interrupt ps-13 mb-13 axi_ad9684_dma/irq
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# DAQ1
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# DAC core
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add_instance axi_ad9122 axi_ad9122
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set_instance_parameter_value axi_ad9122 {ID} {0}
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add_connection sys_clk.clk_reset axi_ad9122.s_axi_reset
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add_connection sys_clk.clk axi_ad9122.s_axi_clock
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add_interface axi_ad9122_device_if conduit end
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set_interface_property axi_ad9122_device_if EXPORT_OF axi_ad9122.device_if
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# DAC unpack
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add_instance util_ad9122_upack util_upack
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set_instance_parameter_value util_ad9122_upack {NUM_OF_CHANNELS} {2}
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set_instance_parameter_value util_ad9122_upack {CHANNEL_DATA_WIDTH} {64}
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add_connection axi_ad9122.if_dac_div_clk util_ad9122_upack.if_dac_clk
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add_connection util_ad9122_upack.dac_ch_0 axi_ad9122.dac_ch_0
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add_connection util_ad9122_upack.dac_ch_1 axi_ad9122.dac_ch_1
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# DAC DMA
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add_instance axi_ad9122_dma axi_dmac
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set_instance_parameter_value axi_ad9122_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9122_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_DEST} {2}
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set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_ad9122_dma {CYCLIC} {1}
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set_instance_parameter_value axi_ad9122_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_ad9122_dma {DMA_LENGTH_WIDTH} {24}
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add_connection sys_clk.clk_reset axi_ad9122_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9122_dma.s_axi_clock
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9122_dma.m_src_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9122_dma.m_src_axi_clock
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add_connection axi_ad9122.if_dac_div_clk axi_ad9122_dma.if_fifo_rd_clk
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add_connection util_ad9122_upack.if_dac_valid axi_ad9122_dma.if_fifo_rd_en
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add_connection axi_ad9122_dma.if_fifo_rd_dout util_ad9122_upack.if_dac_data
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add_connection axi_ad9122_dma.if_fifo_rd_underflow axi_ad9122.if_dac_dunf
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# ADC core
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add_instance axi_ad9684 axi_ad9684
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set_instance_parameter_value axi_ad9684 {OR_STATUS} {0}
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add_connection sys_clk.clk_reset axi_ad9684.s_axi_reset
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add_connection sys_clk.clk axi_ad9684.s_axi_clock
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add_interface axi_ad9684_device_if conduit end
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set_interface_property axi_ad9684_device_if EXPORT_OF axi_ad9684.device_if
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# ADC pack
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add_instance util_ad9684_cpack util_cpack
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set_instance_parameter_value util_ad9684_cpack {NUM_OF_CHANNELS} {2}
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set_instance_parameter_value util_ad9684_cpack {CHANNEL_DATA_WIDTH} {32}
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add_connection sys_clk.clk_reset util_ad9684_cpack.if_adc_rst
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add_connection axi_ad9684.if_adc_clk util_ad9684_cpack.if_adc_clk
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add_connection axi_ad9684.adc_ch_0 util_ad9684_cpack.adc_ch_0
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add_connection axi_ad9684.adc_ch_1 util_ad9684_cpack.adc_ch_1
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# ADC FIFO
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add_instance ad9684_adcfifo util_adcfifo
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set_instance_parameter_value ad9684_adcfifo {ADC_DATA_WIDTH} {64}
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set_instance_parameter_value ad9684_adcfifo {DMA_DATA_WIDTH} {64}
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set_instance_parameter_value ad9684_adcfifo {DMA_ADDRESS_WIDTH} {16}
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add_connection sys_clk.clk_reset ad9684_adcfifo.if_adc_rst
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add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9684_adcfifo.if_adc_rst
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add_connection axi_ad9684.if_adc_clk ad9684_adcfifo.if_adc_clk
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add_connection util_ad9684_cpack.if_adc_valid ad9684_adcfifo.if_adc_wr
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add_connection util_ad9684_cpack.if_adc_data ad9684_adcfifo.if_adc_wdata
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add_connection sys_ddr3_cntrl.emif_usr_clk ad9684_adcfifo.if_dma_clk
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# ADC DMA
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add_instance axi_ad9684_dma axi_dmac
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set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_SRC} {1}
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set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9684_dma {ID} {1}
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set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_ad9684_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9684_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9684_dma {FIFO_SIZE} {16}
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set_instance_parameter_value axi_ad9684_dma {CYCLIC} {0}
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add_connection sys_clk.clk_reset axi_ad9684_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9684_dma.s_axi_clock
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9684_dma.m_dest_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.m_dest_axi_clock
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.if_s_axis_aclk
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add_connection ad9684_adcfifo.if_dma_wr axi_ad9684_dma.if_s_axis_valid
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add_connection ad9684_adcfifo.if_dma_wdata axi_ad9684_dma.if_s_axis_data
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add_connection axi_ad9684_dma.if_s_axis_ready ad9684_adcfifo.if_dma_wready
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add_connection axi_ad9684_dma.if_s_axis_xfer_req ad9684_adcfifo.if_dma_xfer_req
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# IRQ bridge for the CPLD IRQ signal
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add_instance irq_bridge altera_irq_bridge
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set_instance_parameter_value irq_bridge {IRQ_WIDTH} {1}
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add_connection sys_clk.clk_reset irq_bridge.clk_reset
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add_connection sys_clk.clk irq_bridge.clk
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add_interface spi_int conduit end
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set_interface_property spi_int EXPORT_OF irq_bridge.receiver_irq
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# cpu interconnects
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ad_cpu_interconnect 0x44A00000 axi_ad9122.s_axi
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ad_cpu_interconnect 0x44A20000 axi_ad9684.s_axi
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ad_cpu_interconnect 0x44A40000 axi_ad9122_dma.s_axi
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ad_cpu_interconnect 0x44A60000 axi_ad9684_dma.s_axi
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# dma interconnects
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ad_dma_interconnect axi_ad9684_dma.m_dest_axi
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ad_dma_interconnect axi_ad9122_dma.m_src_axi
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# interrupts
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ad_cpu_interrupt 9 irq_bridge.sender0_irq
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ad_cpu_interrupt 10 axi_ad9684_dma.interrupt_sender
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ad_cpu_interrupt 11 axi_ad9122_dma.interrupt_sender
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@ -1,106 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module daq1_spi (
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input spi_csn,
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input spi_clk,
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input spi_mosi,
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output spi_miso,
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inout spi_sdio);
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// device address
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localparam [ 7:0] SPI_SEL_AD9684 = 8'h80;
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localparam [ 7:0] SPI_SEL_AD9122 = 8'h81;
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localparam [ 7:0] SPI_SEL_AD9523 = 8'h82;
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localparam [ 7:0] SPI_SEL_CPLD = 8'h83;
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// internal registers
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reg [ 5:0] spi_count = 6'b0;
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reg spi_rd_wr_n = 1'b0;
|
||||
reg spi_enable = 1'b0;
|
||||
reg [ 7:0] spi_device_addr = 8'b0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire spi_enable_s;
|
||||
|
||||
// check on rising edge and change on falling edge
|
||||
|
||||
assign spi_enable_s = spi_enable & ~spi_csn;
|
||||
|
||||
always @(posedge spi_clk or posedge spi_csn) begin
|
||||
if (spi_csn == 1'b1) begin
|
||||
spi_count <= 6'b0000000;
|
||||
spi_rd_wr_n <= 1'b0;
|
||||
spi_device_addr <= 8'b00000000;
|
||||
end else begin
|
||||
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
|
||||
if (spi_count <= 6'd7) begin
|
||||
spi_device_addr <= {spi_device_addr[6:0], spi_mosi};
|
||||
end
|
||||
if (spi_count == 6'd8) begin
|
||||
spi_rd_wr_n <= spi_mosi;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge spi_clk or posedge spi_csn) begin
|
||||
if (spi_csn == 1'b1) begin
|
||||
spi_enable <= 1'b0;
|
||||
end else begin
|
||||
if (((spi_device_addr == SPI_SEL_AD9684) && (spi_count == 6'd24)) ||
|
||||
((spi_device_addr == SPI_SEL_AD9122) && (spi_count == 6'd16)) ||
|
||||
((spi_device_addr == SPI_SEL_AD9523) && (spi_count == 6'd24)) ||
|
||||
((spi_device_addr == SPI_SEL_CPLD) && (spi_count == 6'd16))) begin
|
||||
spi_enable <= spi_rd_wr_n;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// io logic
|
||||
|
||||
assign spi_miso = spi_sdio;
|
||||
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "adc_fda" LOC = "P6" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "adc_fdb" LOC = "P7" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "adc_pwdn_stby" LOC = "P10" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "adc_spicsn" LOC = "P13" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "adc_status_n" LOC = "P9" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "adc_status_p" LOC = "P8" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "clk_pwdnn" LOC = "P20" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "clk_resetn" LOC = "P25" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "clk_spicsn" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "clk_status1" LOC = "P17" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "clk_status2" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "clk_syncn" LOC = "P24" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "dac_irqn" LOC = "P26" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "dac_resetn" LOC = "P27" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "dac_spicsn" LOC = "P14" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "fmc_irq" LOC = "P2" | IOSTANDARD = LVCMOS25;
|
||||
NET "fmc_spi_csn" LOC = "P5" | IOSTANDARD = LVCMOS25 ;
|
||||
NET "fmc_spi_sclk" LOC = "P4" | IOSTANDARD = LVCMOS25 ;
|
||||
NET "fmc_spi_sdio" LOC = "P1" | IOSTANDARD = LVCMOS25 ;
|
||||
NET "sclk" LOC = "P30" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "sdio" LOC = "P28" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module daq1_cpld (
|
||||
|
||||
// FMC SPI interface
|
||||
|
||||
input fmc_spi_sclk,
|
||||
input fmc_spi_csn,
|
||||
inout fmc_spi_sdio,
|
||||
output fmc_irq,
|
||||
|
||||
// on board SPI interface
|
||||
|
||||
output adc_spicsn,
|
||||
output dac_spicsn,
|
||||
output clk_spicsn,
|
||||
output sclk,
|
||||
inout sdio,
|
||||
|
||||
// control and status lines
|
||||
|
||||
input adc_fda,
|
||||
input adc_fdb,
|
||||
input adc_status_p,
|
||||
input adc_status_n,
|
||||
output adc_pwdn_stby,
|
||||
|
||||
input dac_irqn,
|
||||
output dac_resetn,
|
||||
|
||||
input clk_status1,
|
||||
input clk_status2,
|
||||
output clk_pwdnn,
|
||||
output clk_syncn,
|
||||
output clk_resetn
|
||||
);
|
||||
|
||||
// FMC SPI Selects
|
||||
|
||||
localparam [ 7:0] FMC_SPI_SEL_AD9684 = 8'h80;
|
||||
localparam [ 7:0] FMC_SPI_SEL_AD9122 = 8'h81;
|
||||
localparam [ 7:0] FMC_SPI_SEL_AD9523 = 8'h82;
|
||||
localparam [ 7:0] FMC_SPI_SEL_CPLD = 8'h83;
|
||||
|
||||
// CPLD Register Map Addresses
|
||||
|
||||
localparam [ 6:0] CPLD_VERSION_ADDR = 7'h00;
|
||||
localparam [ 6:0] ADC_CONTROL_ADDR = 7'h10;
|
||||
localparam [ 6:0] DAC_CONTROL_ADDR = 7'h11;
|
||||
localparam [ 6:0] CLK_CONTROL_ADDR = 7'h12;
|
||||
localparam [ 6:0] IRQ_MASK_ADDR = 7'h13;
|
||||
localparam [ 6:0] ADC_STATUS_ADDR = 7'h20;
|
||||
localparam [ 6:0] DAC_STATUS_ADDR = 7'h21;
|
||||
localparam [ 6:0] CLK_STATUS_ADDR = 7'h22;
|
||||
|
||||
localparam [ 7:0] CPLD_VERSION = 8'h11;
|
||||
|
||||
// Internal Registers/Signals
|
||||
|
||||
reg [ 7:0] fmc_spi_dev_sel = 8'b0;
|
||||
reg [ 7:0] fmc_cpld_addr = 8'b0;
|
||||
reg [ 5:0] fmc_spi_counter = 6'b0;
|
||||
reg fmc_spi_csn_enb = 1'b1;
|
||||
|
||||
reg [ 7:0] adc_control = 8'b0;
|
||||
reg [ 7:0] dac_control = 8'b0;
|
||||
reg [ 7:0] clk_control = 8'b0;
|
||||
|
||||
reg [ 7:0] adc_status = 8'b0;
|
||||
reg [ 7:0] dac_status = 8'b0;
|
||||
reg [ 7:0] clk_status = 8'b0;
|
||||
|
||||
reg cpld_to_fpga = 1'b0;
|
||||
reg [ 7:0] cpld_rdata = 8'b0;
|
||||
reg cpld_rdata_bit = 1'b0;
|
||||
reg [ 2:0] cpld_rdata_index = 3'h0;
|
||||
reg [ 7:0] cpld_wdata = 8'b0;
|
||||
reg [ 7:0] cpld_irq_mask = 8'b0;
|
||||
reg [ 7:0] cpld_irq = 8'b0;
|
||||
|
||||
wire rdnwr;
|
||||
wire cpld_rdata_s;
|
||||
|
||||
// SCLK counter for control signals
|
||||
|
||||
always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
|
||||
if (fmc_spi_csn == 1'b1) begin
|
||||
fmc_spi_dev_sel <= 8'h0;
|
||||
fmc_cpld_addr <= 8'h0;
|
||||
end else begin
|
||||
if (fmc_spi_counter <= 7) begin
|
||||
fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio};
|
||||
end
|
||||
if (fmc_spi_counter <= 15) begin
|
||||
fmc_cpld_addr <= {fmc_cpld_addr[6:0], fmc_spi_sdio};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// chip select control
|
||||
|
||||
assign adc_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9684) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
|
||||
assign dac_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9122) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
|
||||
assign clk_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9523) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
|
||||
assign cpld_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_CPLD) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
|
||||
|
||||
// SPI control and data
|
||||
|
||||
assign sdio = cpld_to_fpga ? 1'bZ : fmc_spi_sdio;
|
||||
assign fmc_spi_sdio = cpld_to_fpga ? cpld_rdata_s : 1'bZ ;
|
||||
assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
|
||||
assign rdnwr = fmc_cpld_addr[7];
|
||||
|
||||
assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
|
||||
|
||||
always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
|
||||
if (fmc_spi_csn == 1'b1) begin
|
||||
fmc_spi_counter <= 6'h0;
|
||||
cpld_to_fpga <= 1'b0;
|
||||
fmc_spi_csn_enb <= 1'b1;
|
||||
end else begin
|
||||
fmc_spi_counter <= (fmc_spi_counter <= 6'h3F) ? fmc_spi_counter + 1 : fmc_spi_counter;
|
||||
fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0;
|
||||
if (adc_spicsn & clk_spicsn) begin
|
||||
cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0;
|
||||
end else begin
|
||||
cpld_to_fpga <= (fmc_spi_counter >= 23) ? rdnwr : 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Internal register read access
|
||||
|
||||
always @(fmc_cpld_addr) begin
|
||||
case (fmc_cpld_addr[6:0])
|
||||
CPLD_VERSION_ADDR :
|
||||
cpld_rdata <= CPLD_VERSION;
|
||||
ADC_CONTROL_ADDR :
|
||||
cpld_rdata <= adc_pwdn_stby;
|
||||
DAC_CONTROL_ADDR :
|
||||
cpld_rdata <= dac_resetn;
|
||||
CLK_CONTROL_ADDR :
|
||||
cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn};
|
||||
IRQ_MASK_ADDR:
|
||||
cpld_rdata <= cpld_irq_mask;
|
||||
ADC_STATUS_ADDR :
|
||||
cpld_rdata <= {adc_status_p, adc_fdb, adc_fda};
|
||||
DAC_STATUS_ADDR :
|
||||
cpld_rdata <= dac_irqn;
|
||||
CLK_STATUS_ADDR :
|
||||
cpld_rdata <= {clk_status2, clk_status1};
|
||||
default:
|
||||
cpld_rdata <= 8'hFA;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
|
||||
if (fmc_spi_csn == 1'b1) begin
|
||||
cpld_rdata_bit <= cpld_rdata[7];
|
||||
cpld_rdata_index <= 3'h6;
|
||||
end else begin
|
||||
if (cpld_to_fpga == 1'b1) begin
|
||||
cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
|
||||
cpld_rdata_index <= cpld_rdata_index - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Internal register write access
|
||||
|
||||
always @(cpld_to_fpga, cpld_spicsn, fmc_spi_counter) begin
|
||||
if ((cpld_to_fpga == 1'b0) &&
|
||||
(cpld_spicsn == 1'b0) &&
|
||||
(fmc_spi_counter == 8'h18)) begin
|
||||
case (fmc_cpld_addr[6:0])
|
||||
ADC_CONTROL_ADDR :
|
||||
adc_control <= cpld_wdata;
|
||||
DAC_CONTROL_ADDR :
|
||||
dac_control <= cpld_wdata;
|
||||
CLK_CONTROL_ADDR :
|
||||
clk_control <= cpld_wdata;
|
||||
IRQ_MASK_ADDR:
|
||||
cpld_irq_mask <= cpld_wdata;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
|
||||
if (fmc_spi_csn == 1'b1) begin
|
||||
cpld_wdata <= 8'h0;
|
||||
end else begin
|
||||
if (fmc_spi_counter >= 16) begin
|
||||
cpld_wdata <= {cpld_wdata[6:0], fmc_spi_sdio};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// input/output logic
|
||||
|
||||
// AD9648
|
||||
|
||||
assign adc_pwdn_stby = adc_control[0];
|
||||
|
||||
// AD9122
|
||||
|
||||
assign dac_resetn = dac_control[0];
|
||||
|
||||
// AD9523-1
|
||||
|
||||
assign clk_pwdnn = clk_control[0];
|
||||
assign clk_resetn = clk_control[1];
|
||||
assign clk_syncn = clk_control[2];
|
||||
|
||||
// interrupt logic
|
||||
|
||||
always @(*) begin
|
||||
cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda};
|
||||
end
|
||||
|
||||
assign fmc_irq = |(~cpld_irq_mask & cpld_irq);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,241 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="daq1_cpld.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="daq1_cpld.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc2c64a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="CoolRunner2 CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|daq1_cpld" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="daq1_cpld.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/daq1_cpld" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="daq1_cpld" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="QFG48" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="daq1_cpld_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="daq1_cpld_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="daq1_cpld_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="daq1_cpld_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/daq1_cpld_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.daq1_cpld_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.daq1_cpld_test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="daq1_cpld.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Ground" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|daq1_cpld_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="daq1_cpld" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-12-22T16:59:48" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E3A619140B8D441CB02D709A04E40C60" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := daq1_zc706
|
||||
|
||||
M_DEPS += ../common/daq1_spi.v
|
||||
M_DEPS += ../common/daq1_bd.tcl
|
||||
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
|
||||
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
|
||||
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
|
||||
M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl
|
||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
|
||||
LIB_DEPS += axi_ad9122
|
||||
LIB_DEPS += axi_ad9684
|
||||
LIB_DEPS += axi_clkgen
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += axi_hdmi_tx
|
||||
LIB_DEPS += axi_spdif_tx
|
||||
LIB_DEPS += util_cpack
|
||||
LIB_DEPS += util_upack
|
||||
LIB_DEPS += xilinx/axi_adcfifo
|
||||
|
||||
include ../../scripts/project-xilinx.mk
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
|
||||
set adc_fifo_name axi_ad9684_fifo
|
||||
set adc_fifo_address_width 18
|
||||
set adc_data_width 64
|
||||
set adc_dma_data_width 64
|
||||
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
|
||||
source ../common/daq1_bd.tcl
|
||||
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
|
||||
# daq1
|
||||
|
||||
set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## G02 FMC_LPC_CLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## G03 FMC_LPC_CLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p] ; ## G27 FMC_LPC_LA25_P
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n] ; ## G28 FMC_LPC_LA25_N
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p] ; ## H37 FMC_LPC_LA32_P
|
||||
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n] ; ## H38 FMC_LPC_LA32_N
|
||||
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]] ; ## H19 FMC_LPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]] ; ## H20 FMC_LPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]] ; ## G21 FMC_LPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]] ; ## G22 FMC_LPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]] ; ## H22 FMC_LPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]] ; ## H23 FMC_LPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]] ; ## D20 FMC_LPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]] ; ## D21 FMC_LPC_LA17_CC_N
|
||||
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]] ; ## D23 FMC_LPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]] ; ## D24 FMC_LPC_LA23_N
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]] ; ## G24 FMC_LPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]] ; ## G25 FMC_LPC_LA22_N
|
||||
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]] ; ## C22 FMC_LPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]] ; ## C23 FMC_LPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]] ; ## H25 FMC_LPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]] ; ## H26 FMC_LPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]] ; ## D26 FMC_LPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]] ; ## D27 FMC_LPC_LA26_N
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]] ; ## H28 FMC_LPC_LA24_P
|
||||
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]] ; ## H29 FMC_LPC_LA24_N
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]] ; ## C26 FMC_LPC_LA27_P
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]] ; ## C27 FMC_LPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]] ; ## G30 FMC_LPC_LA29_P
|
||||
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]] ; ## G31 FMC_LPC_LA29_N
|
||||
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]] ; ## H31 FMC_LPC_LA28_P
|
||||
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]] ; ## H32 FMC_LPC_LA28_N
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]] ; ## G33 FMC_LPC_LA31_P
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]] ; ## G34 FMC_LPC_LA31_N
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]] ; ## H34 FMC_LPC_LA30_P
|
||||
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]] ; ## H35 FMC_LPC_LA30_N
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]] ; ## G36 FMC_LPC_LA33_P
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]] ; ## G37 FMC_LPC_LA33_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P
|
||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N
|
||||
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## C14 FMC_LPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## C15 FMC_LPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C18 FMC_LPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C19 FMC_LPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## D17 FMC_LPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## D18 FMC_LPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H16 FMC_LPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H17 FMC_LPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## G15 FMC_LPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## G16 FMC_LPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D14 FMC_LPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D15 FMC_LPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N
|
||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N
|
||||
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D11 FMC_LPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D12 FMC_LPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## H10 FMC_LPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## H11 FMC_LPC_LA04_N
|
||||
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## G09 FMC_LPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## G10 FMC_LPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## C10 FMC_LPC_LA06_P
|
||||
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## C11 FMC_LPC_LA06_N
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## H07 FMC_LPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## H08 FMC_LPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## D08 FMC_LPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## D09 FMC_LPC_LA01_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## H05 FMC_LPC_CLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H04 FMC_LPC_CLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G18 FMC_LPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports spi_int] ; ## G19 FMC_LPC_LA16_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
|
||||
create_clock -name adc_clk_in -period 2.00 [get_ports adc_clk_in_p]
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_xilinx daq1_zc706
|
||||
adi_project_files daq1_zc706 [list \
|
||||
"../common/daq1_spi.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
|
||||
"system_top.v" ]
|
||||
|
||||
adi_project_run daq1_zc706
|
||||
|
||||
|
|
@ -1,235 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [14:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [23:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
|
||||
input dac_clk_in_p,
|
||||
input dac_clk_in_n,
|
||||
output dac_clk_out_p,
|
||||
output dac_clk_out_n,
|
||||
output dac_frame_out_p,
|
||||
output dac_frame_out_n,
|
||||
output [15:0] dac_data_out_p,
|
||||
output [15:0] dac_data_out_n,
|
||||
|
||||
input adc_clk_in_p,
|
||||
input adc_clk_in_n,
|
||||
input [13:0] adc_data_in_p,
|
||||
input [13:0] adc_data_in_n,
|
||||
|
||||
output spi_clk,
|
||||
output spi_csn,
|
||||
inout spi_sdio,
|
||||
input spi_int,
|
||||
|
||||
input sys_rst,
|
||||
input sys_clk_p,
|
||||
input sys_clk_n,
|
||||
|
||||
output [13:0] ddr3_addr,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_cas_n,
|
||||
output [ 0:0] ddr3_ck_n,
|
||||
output [ 0:0] ddr3_ck_p,
|
||||
output [ 0:0] ddr3_cke,
|
||||
output [ 0:0] ddr3_cs_n,
|
||||
output [ 7:0] ddr3_dm,
|
||||
inout [63:0] ddr3_dq,
|
||||
inout [ 7:0] ddr3_dqs_n,
|
||||
inout [ 7:0] ddr3_dqs_p,
|
||||
output [ 0:0] ddr3_odt,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_we_n);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire spi_mosi;
|
||||
wire spi_miso;
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd (
|
||||
.dio_t (gpio_t[14:0]),
|
||||
.dio_i (gpio_o[14:0]),
|
||||
.dio_o (gpio_i[14:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
daq1_spi i_spi (
|
||||
.spi_csn (spi_csn),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_sdio (spi_sdio));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.sys_clk_clk_n (sys_clk_n),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_rst (sys_rst),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
.ddr3_ck_n (ddr3_ck_n),
|
||||
.ddr3_ck_p (ddr3_ck_p),
|
||||
.ddr3_cke (ddr3_cke),
|
||||
.ddr3_cs_n (ddr3_cs_n),
|
||||
.ddr3_dm (ddr3_dm),
|
||||
.ddr3_dq (ddr3_dq),
|
||||
.ddr3_dqs_n (ddr3_dqs_n),
|
||||
.ddr3_dqs_p (ddr3_dqs_p),
|
||||
.ddr3_odt (ddr3_odt),
|
||||
.ddr3_ras_n (ddr3_ras_n),
|
||||
.ddr3_reset_n (ddr3_reset_n),
|
||||
.ddr3_we_n (ddr3_we_n),
|
||||
.adc_clk_in_n (adc_clk_in_n),
|
||||
.adc_clk_in_p (adc_clk_in_p),
|
||||
.adc_data_in_n (adc_data_in_n),
|
||||
.adc_data_in_p (adc_data_in_p),
|
||||
.dac_clk_in_n (dac_clk_in_n),
|
||||
.dac_clk_in_p (dac_clk_in_p),
|
||||
.dac_clk_out_n (dac_clk_out_n),
|
||||
.dac_clk_out_p (dac_clk_out_p),
|
||||
.dac_data_out_n (dac_data_out_n),
|
||||
.dac_data_out_p (dac_data_out_p),
|
||||
.dac_frame_out_n (dac_frame_out_n),
|
||||
.dac_frame_out_p (dac_frame_out_p),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.spi_int (spi_int));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := daq1_zed
|
||||
|
||||
M_DEPS += ../common/daq1_spi.v
|
||||
M_DEPS += ../common/daq1_bd.tcl
|
||||
M_DEPS += ../../common/zed/zed_system_constr.xdc
|
||||
M_DEPS += ../../common/zed/zed_system_bd.tcl
|
||||
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
|
||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
|
||||
LIB_DEPS += axi_ad9122
|
||||
LIB_DEPS += axi_ad9684
|
||||
LIB_DEPS += axi_clkgen
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += axi_hdmi_tx
|
||||
LIB_DEPS += axi_i2s_adi
|
||||
LIB_DEPS += axi_spdif_tx
|
||||
LIB_DEPS += util_adcfifo
|
||||
LIB_DEPS += util_cpack
|
||||
LIB_DEPS += util_i2c_mixer
|
||||
LIB_DEPS += util_upack
|
||||
|
||||
include ../../scripts/project-xilinx.mk
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
|
||||
set adc_fifo_name axi_ad9684_fifo
|
||||
set adc_fifo_address_width 10
|
||||
set adc_data_width 64
|
||||
set adc_dma_data_width 64
|
||||
|
||||
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
source ../common/daq1_bd.tcl
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
|
||||
# daq1
|
||||
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## G02 FMC_LPC_CLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## G03 FMC_LPC_CLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p] ; ## G27 FMC_LPC_LA25_P
|
||||
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n] ; ## G28 FMC_LPC_LA25_N
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p] ; ## H37 FMC_LPC_LA32_P
|
||||
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n] ; ## H38 FMC_LPC_LA32_N
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]] ; ## H19 FMC_LPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]] ; ## H20 FMC_LPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]] ; ## G21 FMC_LPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]] ; ## G22 FMC_LPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]] ; ## H22 FMC_LPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]] ; ## H23 FMC_LPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]] ; ## D20 FMC_LPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]] ; ## D21 FMC_LPC_LA17_CC_N
|
||||
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]] ; ## D23 FMC_LPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]] ; ## D24 FMC_LPC_LA23_N
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]] ; ## G24 FMC_LPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]] ; ## G25 FMC_LPC_LA22_N
|
||||
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]] ; ## C22 FMC_LPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]] ; ## C23 FMC_LPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]] ; ## H25 FMC_LPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]] ; ## H26 FMC_LPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]] ; ## D26 FMC_LPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]] ; ## D27 FMC_LPC_LA26_N
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]] ; ## A18 FMC_LPC_LA24_P
|
||||
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]] ; ## H29 FMC_LPC_LA24_N
|
||||
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]] ; ## C26 FMC_LPC_LA27_P
|
||||
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]] ; ## C27 FMC_LPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]] ; ## G30 FMC_LPC_LA29_P
|
||||
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]] ; ## G31 FMC_LPC_LA29_N
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]] ; ## H31 FMC_LPC_LA28_P
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]] ; ## H32 FMC_LPC_LA28_N
|
||||
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]] ; ## G33 FMC_LPC_LA31_P
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]] ; ## G34 FMC_LPC_LA31_N
|
||||
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]] ; ## H34 FMC_LPC_LA30_P
|
||||
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]] ; ## H35 FMC_LPC_LA30_N
|
||||
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]] ; ## G36 FMC_LPC_LA33_P
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]] ; ## G37 FMC_LPC_LA33_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N
|
||||
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## C14 FMC_LPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## C15 FMC_LPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C18 FMC_LPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C19 FMC_LPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## D17 FMC_LPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## D18 FMC_LPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H16 FMC_LPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H17 FMC_LPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## G15 FMC_LPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## G16 FMC_LPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D14 FMC_LPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D15 FMC_LPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N
|
||||
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D11 FMC_LPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D12 FMC_LPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## H10 FMC_LPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## H11 FMC_LPC_LA04_N
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## G09 FMC_LPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## G10 FMC_LPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## C10 FMC_LPC_LA06_P
|
||||
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## C11 FMC_LPC_LA06_N
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## H07 FMC_LPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## H08 FMC_LPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## D08 FMC_LPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## D09 FMC_LPC_LA01_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H04 FMC_LPC_CLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## H05 FMC_LPC_CLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G18 FMC_LPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports spi_int] ; ## G19 FMC_LPC_LA16_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name dac_clk_in -period 2.222 [get_ports dac_clk_in_p]
|
||||
create_clock -name adc_clk_in -period 2.222 [get_ports adc_clk_in_p]
|
||||
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_xilinx daq1_zed
|
||||
adi_project_files daq1_zed [list \
|
||||
"../common/daq1_spi.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
|
||||
"system_top.v" ]
|
||||
|
||||
adi_project_run daq1_zed
|
||||
|
||||
|
|
@ -1,236 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
input dac_clk_in_p,
|
||||
input dac_clk_in_n,
|
||||
output dac_clk_out_p,
|
||||
output dac_clk_out_n,
|
||||
output dac_frame_out_p,
|
||||
output dac_frame_out_n,
|
||||
output [15:0] dac_data_out_p,
|
||||
output [15:0] dac_data_out_n,
|
||||
|
||||
input adc_clk_in_p,
|
||||
input adc_clk_in_n,
|
||||
input [13:0] adc_data_in_p,
|
||||
input [13:0] adc_data_in_n,
|
||||
|
||||
output spi_clk,
|
||||
output spi_csn,
|
||||
inout spi_sdio,
|
||||
input spi_int);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire spi_mosi;
|
||||
wire spi_miso;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(32)) i_gpio_bd (
|
||||
.dio_t (gpio_t[31:0]),
|
||||
.dio_i (gpio_o[31:0]),
|
||||
.dio_o (gpio_i[31:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
daq1_spi i_spi (
|
||||
.spi_csn (spi_csn),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_sdio (spi_sdio));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
|
||||
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
|
||||
.dio_i (iic_mux_scl_o_s),
|
||||
.dio_o (iic_mux_scl_i_s),
|
||||
.dio_p (iic_mux_scl));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
|
||||
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
|
||||
.dio_i (iic_mux_sda_o_s),
|
||||
.dio_o (iic_mux_sda_i_s),
|
||||
.dio_p (iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.adc_clk_in_n (adc_clk_in_n),
|
||||
.adc_clk_in_p (adc_clk_in_p),
|
||||
.adc_data_in_n (adc_data_in_n),
|
||||
.adc_data_in_p (adc_data_in_p),
|
||||
.dac_clk_in_n (dac_clk_in_n),
|
||||
.dac_clk_in_p (dac_clk_in_p),
|
||||
.dac_clk_out_n (dac_clk_out_n),
|
||||
.dac_clk_out_p (dac_clk_out_p),
|
||||
.dac_data_out_n (dac_data_out_n),
|
||||
.dac_data_out_p (dac_data_out_p),
|
||||
.dac_frame_out_n (dac_frame_out_n),
|
||||
.dac_frame_out_p (dac_frame_out_p),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.spi_int (spi_int));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue