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axi_ad7616: Add burst counter to the parallel interface 

With this counter the parallel logic supports the burst sequencer.
main
Istvan Csomortani 2016-06-29 14:17:28 +03:00
parent e6494b9a74
commit 18e28b01fd
3 changed files with 31 additions and 7 deletions
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4
library/axi_ad7616/axi_ad7616.v
View File

@ -178,7 +178,7 @@ module axi_ad7616 (
wire [15:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [ 4:0] burst_length_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
@ -441,6 +441,7 @@ module axi_ad7616 (
.adc_valid (adc_valid),
.adc_sync (adc_sync),
.end_of_conv (trigger_s),
.burst_length(burst_length_s),
.clk (up_clk),
.rstn (up_rstn),
.rd_req (rd_req_s),
@ -459,6 +460,7 @@ module axi_ad7616 (
) i_ad7616_control (
.cnvst (cnvst),
.busy (busy),
.up_burst_length (burst_length_s),
.up_read_data (rd_data_s),
.up_read_valid (rd_valid_s),
.up_write_data (wr_data_s),

18
library/axi_ad7616/axi_ad7616_control.v
View File

@ -52,6 +52,7 @@ module axi_ad7616_control (
up_read_req,
up_write_req,
up_burst_length,
end_of_conv,
// bus interface
@ -82,6 +83,7 @@ module axi_ad7616_control (
input busy;
output end_of_conv;
output [ 4:0] up_burst_length;
input [15:0] up_read_data;
input up_read_valid;
@ -111,6 +113,7 @@ module axi_ad7616_control (
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_conv_rate = 32'b0;
reg [ 4:0] up_burst_length = 5'h0;
reg [15:0] up_write_data = 16'h0;
reg [31:0] cnvst_counter = 32'b0;
@ -146,6 +149,7 @@ module axi_ad7616_control (
up_resetn <= 1'b0;
up_cnvst_en <= 1'b0;
up_conv_rate <= 32'b0;
up_burst_length <= 5'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@ -158,18 +162,21 @@ module axi_ad7616_control (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_conv_rate <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_burst_length <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_write_data <= up_wdata;
end
end
end
assign up_write_req = (up_waddr[7:0] == 8'h13) ? up_wreq_s : 1'h0;
assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
// processor read interface
assign up_rack_s = (up_raddr[7:0] == 8'h12) ? up_read_valid_s : up_rreq_s;
assign up_read_req = (up_raddr[7:0] == 8'h12) ? up_rreq_s : 1'b0;
assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
@ -185,7 +192,8 @@ module axi_ad7616_control (
8'h03 : up_rdata = IF_TYPE;
8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
8'h11 : up_rdata = up_conv_rate;
8'h12 : up_rdata = up_read_data_s;
8'h12 : up_rdata = {27'b0, up_burst_length};
8'h13 : up_rdata = up_read_data_s;
endcase
end
end

16
library/axi_ad7616/axi_ad7616_pif.v
View File

@ -59,6 +59,7 @@ module axi_ad7616_pif (
// end of convertion
end_of_conv,
burst_length,
// register access
@ -83,6 +84,7 @@ module axi_ad7616_pif (
output wr_n;
input end_of_conv;
input [ 4:0] burst_length;
input clk;
input rstn;
@ -111,6 +113,7 @@ module axi_ad7616_pif (
reg [ 2:0] transfer_state = 3'h0;
reg [ 2:0] transfer_state_next = 3'h0;
reg [ 1:0] width_counter = 2'h0;
reg [ 4:0] burst_counter = 5'h0;
reg wr_req_d = 1'h0;
reg rd_req_d = 1'h0;
@ -154,6 +157,17 @@ module axi_ad7616_pif (
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
burst_counter <= 2'h0;
end else begin
if (transfer_state == CS_HIGH)
burst_counter <= burst_counter + 1;
else if (transfer_state == IDLE)
burst_counter <= 5'h0;
end
end
always @(negedge clk) begin
if (transfer_state == IDLE) begin
wr_req_d <= wr_req;
@ -186,7 +200,7 @@ module axi_ad7616_pif (
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
end
CS_HIGH : begin
transfer_state_next <= IDLE;
transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
end
default : begin
transfer_state_next <= IDLE;