cn0540: Initial commit
Stanca Pop
István Csomortáni
parent
03ab28d7bf
commit
193fce338d
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@ -0,0 +1,6 @@
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####################################################################################
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## Copyright 2019-2020(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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@ -0,0 +1,109 @@
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc_spi
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540
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create_bd_port -dir I adc_data_ready
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ad_ip_instance axi_iic axi_iic_cn0540
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ad_connect iic_cn0540 axi_iic_cn0540/iic
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# create a SPI Engine architecture for ADC
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create_bd_cell -type hier spi_adc
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current_bd_instance /spi_adc
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type clk spi_clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I drdy
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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# DATA_WIDTH is set to 32
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH 32
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_instance axi_spi_engine axi_regmap
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ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH 32
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ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH 32
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH 32
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ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect spi_clk offload/spi_clk
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ad_connect spi_clk offload/ctrl_clk
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ad_connect spi_clk execution/clk
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ad_connect clk axi_regmap/s_axi_aclk
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ad_connect spi_clk axi_regmap/spi_clk
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ad_connect spi_clk interconnect/clk
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ad_connect axi_regmap/spi_resetn offload/spi_resetn
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ad_connect axi_regmap/spi_resetn execution/resetn
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ad_connect axi_regmap/spi_resetn interconnect/resetn
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ad_connect drdy offload/trigger
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ad_connect resetn axi_regmap/s_axi_aresetn
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ad_connect irq axi_regmap/irq
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current_bd_instance /
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ad_connect adc_data_ready spi_adc/drdy
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# dma for the ADC
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ad_ip_instance axi_dmac axi_cn0540_dma
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_cn0540_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_cn0540_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_cn0540_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_cn0540_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect $sys_cpu_clk spi_adc/clk
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ad_connect $sys_cpu_resetn spi_adc/resetn
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ad_connect $sys_cpu_resetn axi_cn0540_dma/m_dest_axi_aresetn
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ad_connect spi_adc/m_spi adc_spi
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ad_connect $sys_dma_clk spi_adc/spi_clk
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ad_connect axi_cn0540_dma/s_axis spi_adc/M_AXIS_SAMPLE
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# AXI address definitions
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ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_cn0540_dma
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ad_cpu_interconnect 0x44a40000 axi_iic_cn0540
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ad_connect $sys_dma_clk axi_cn0540_dma/s_axis_aclk
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt
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ad_cpu_interrupt "ps-11" "mb-11" spi_adc/irq
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# memory interconnects
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ad_mem_hp0_interconnect $sys_cpu_clk axi_cn0540_dma/m_dest_axi
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@ -0,0 +1,22 @@
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####################################################################################
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## Copyright 2019-2020(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := cn0540_coraz7s
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M_DEPS += ../common/cn0540_bd.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
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M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += spi_engine/axi_spi_engine
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LIB_DEPS += spi_engine/spi_engine_execution
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LIB_DEPS += spi_engine/spi_engine_interconnect
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LIB_DEPS += spi_engine/spi_engine_offload
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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set sys_dma_clk [get_bd_nets sys_dma_clk]
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source ../common/cn0540_bd.tcl
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@ -0,0 +1,25 @@
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# SPI interface
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports cn0540_spi_sclk] ; ## CK_IO13
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports cn0540_spi_miso] ; ## CK_IO12
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports cn0540_spi_mosi] ; ## CK_IO11
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set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports cn0540_spi_cs] ; ## CK_IO10
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# reset and GPIO signals
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set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports cn0540_shutdown] ; ## CK_IO9
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set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports cn0540_reset_adc] ; ## CK_IO7
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports cn0540_csb_aux] ; ## CK_IO5
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports cn0540_sw_ff] ; ## CK_IO4
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set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy_aux] ; ## CK_IO3
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set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports cn0540_blue_led] ; ## CK_IO1
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set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports cn0540_yellow_led] ; ## CK_IO0
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# syncronization and timing
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set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports cn0540_sync_in] ; ## CK_IO6
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set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy] ; ## CK_IO2
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set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports cn0540_scl] ; ## CK_SCL
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set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports cn0540_sda] ; ## CK_SDA
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@ -0,0 +1,15 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project cn0540_coraz7s
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adi_project_files cn0540_coraz7s [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
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#adi_project_run cn0540_coraz7s
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@ -0,0 +1,184 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [1:0] btn,
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inout [5:0] led,
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inout cn0540_scl,
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inout cn0540_sda,
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inout cn0540_shutdown,
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inout cn0540_reset_adc,
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inout cn0540_csb_aux,
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inout cn0540_sw_ff,
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inout cn0540_drdy_aux,
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inout cn0540_blue_led,
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inout cn0540_yellow_led,
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inout cn0540_sync_in,
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input cn0540_spi_miso,
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output cn0540_spi_mosi,
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output cn0540_spi_sclk,
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output cn0540_spi_cs,
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inout cn0540_drdy);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_buttons (
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.dio_t(gpio_t[1:0]),
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.dio_i(gpio_o[1:0]),
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.dio_o(gpio_i[1:0]),
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.dio_p(btn));
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ad_iobuf #(
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.DATA_WIDTH(6)
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) i_iobuf_leds (
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.dio_t(gpio_t[7:2]),
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.dio_i(gpio_o[7:2]),
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.dio_o(gpio_i[7:2]),
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.dio_p(led));
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assign gpio_i[31:8] = gpio_o[31:8];
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ad_iobuf #(
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.DATA_WIDTH(9)
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) i_iobuf_cn0540_gpio (
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.dio_t(gpio_t[40:32]),
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.dio_i(gpio_o[40:32]),
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.dio_o(gpio_i[40:32]),
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.dio_p({
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cn0540_shutdown,
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cn0540_reset_adc,
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cn0540_csb_aux,
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cn0540_sw_ff,
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cn0540_drdy_aux,
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cn0540_blue_led,
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cn0540_yellow_led,
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cn0540_sync_in,
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cn0540_drdy}));
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assign gpio_i[63:41] = gpio_o[63:41];
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.adc_spi_sdo (cn0540_spi_mosi),
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.adc_spi_sdo_t (),
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.adc_spi_sdi (cn0540_spi_miso),
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.adc_spi_cs (cn0540_spi_cs),
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.adc_spi_sclk (cn0540_spi_sclk),
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.adc_data_ready (cn0540_drdy),
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.iic_cn0540_scl_io (cn0540_scl),
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.iic_cn0540_sda_io (cn0540_sda),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (),
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.spi0_csn_0_o (),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (1'b0),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o());
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -37,7 +37,7 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 40.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
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|
|
@ -52,34 +52,34 @@ ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
|
|||
|
||||
ad_ip_instance proc_sys_reset sys_rstgen
|
||||
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
ad_ip_instance proc_sys_reset sys_200m_rstgen
|
||||
ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
ad_ip_instance proc_sys_reset sys_dma_rstgen
|
||||
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
|
||||
# system reset/clock definitions
|
||||
|
||||
ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
|
||||
ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
|
||||
ad_connect sys_dma_clk sys_ps7/FCLK_CLK1
|
||||
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
|
||||
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
|
||||
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
|
||||
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
|
||||
ad_connect sys_200m_reset sys_200m_rstgen/peripheral_reset
|
||||
ad_connect sys_200m_resetn sys_200m_rstgen/peripheral_aresetn
|
||||
ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk
|
||||
ad_connect sys_200m_rstgen/ext_reset_in sys_ps7/FCLK_RESET1_N
|
||||
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
|
||||
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
|
||||
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
|
||||
ad_connect sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET1_N
|
||||
|
||||
# generic system clocks pointers
|
||||
|
||||
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
|
||||
set sys_dma_clk [get_bd_nets sys_200m_clk]
|
||||
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
|
||||
set sys_dma_clk [get_bd_nets sys_dma_clk]
|
||||
set sys_iodelay_clk [get_bd_nets sys_dma_clk]
|
||||
|
||||
set sys_cpu_reset [get_bd_nets sys_cpu_reset]
|
||||
set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
|
||||
set sys_dma_reset [get_bd_nets sys_200m_reset]
|
||||
set sys_dma_resetn [get_bd_nets sys_200m_resetn]
|
||||
set sys_iodelay_reset [get_bd_nets sys_200m_reset]
|
||||
set sys_iodelay_resetn [get_bd_nets sys_200m_resetn]
|
||||
set sys_dma_reset [get_bd_nets sys_dma_reset]
|
||||
set sys_dma_resetn [get_bd_nets sys_dma_resetn]
|
||||
set sys_iodelay_reset [get_bd_nets sys_dma_reset]
|
||||
set sys_iodelay_resetn [get_bd_nets sys_dma_resetn]
|
||||
|
||||
# interface connections
|
||||
|
||||
|
|
@ -143,3 +143,6 @@ ad_connect sys_concat_intc/In0 GND
|
|||
# interconnects and address mapping
|
||||
|
||||
ad_cpu_interconnect 0x45000000 axi_sysid_0
|
||||
|
||||
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue