From 193fce338d7bbd787e081c868be00df92fcda35d Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 18 May 2020 10:49:28 +0300 Subject: [PATCH] cn0540: Initial commit --- projects/cn0540/Makefile | 6 + projects/cn0540/common/cn0540_bd.tcl | 109 +++++++++++ projects/cn0540/coraz7s/Makefile | 22 +++ projects/cn0540/coraz7s/system_bd.tcl | 14 ++ projects/cn0540/coraz7s/system_constr.xdc | 25 +++ projects/cn0540/coraz7s/system_project.tcl | 15 ++ projects/cn0540/coraz7s/system_top.v | 184 ++++++++++++++++++ projects/common/coraz7s/coraz7s_system_bd.tcl | 31 +-- 8 files changed, 392 insertions(+), 14 deletions(-) create mode 100755 projects/cn0540/Makefile create mode 100755 projects/cn0540/common/cn0540_bd.tcl create mode 100755 projects/cn0540/coraz7s/Makefile create mode 100755 projects/cn0540/coraz7s/system_bd.tcl create mode 100755 projects/cn0540/coraz7s/system_constr.xdc create mode 100755 projects/cn0540/coraz7s/system_project.tcl create mode 100755 projects/cn0540/coraz7s/system_top.v diff --git a/projects/cn0540/Makefile b/projects/cn0540/Makefile new file mode 100755 index 000000000..e3b0da070 --- /dev/null +++ b/projects/cn0540/Makefile @@ -0,0 +1,6 @@ +#################################################################################### +## Copyright 2019-2020(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/cn0540/common/cn0540_bd.tcl b/projects/cn0540/common/cn0540_bd.tcl new file mode 100755 index 000000000..5faa6eb46 --- /dev/null +++ b/projects/cn0540/common/cn0540_bd.tcl @@ -0,0 +1,109 @@ + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc_spi +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540 + +create_bd_port -dir I adc_data_ready + + +ad_ip_instance axi_iic axi_iic_cn0540 +ad_connect iic_cn0540 axi_iic_cn0540/iic + +# create a SPI Engine architecture for ADC + +create_bd_cell -type hier spi_adc +current_bd_instance /spi_adc + + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type clk spi_clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir I drdy + create_bd_pin -dir O irq + create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE + + # DATA_WIDTH is set to 32 + + ad_ip_instance spi_engine_execution execution + ad_ip_parameter execution CONFIG.DATA_WIDTH 32 + ad_ip_parameter execution CONFIG.NUM_OF_CS 1 + + ad_ip_instance axi_spi_engine axi_regmap + ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH 32 + ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1 + ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK 1 + + ad_ip_instance spi_engine_offload offload + ad_ip_parameter offload CONFIG.DATA_WIDTH 32 + ad_ip_parameter offload CONFIG.ASYNC_TRIG 1 + ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1 + + ad_ip_instance spi_engine_interconnect interconnect + ad_ip_parameter interconnect CONFIG.DATA_WIDTH 32 + + ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl + ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl + ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl + ad_connect interconnect/m_ctrl execution/ctrl + ad_connect offload/offload_sdi M_AXIS_SAMPLE + + ad_connect execution/spi m_spi + + ad_connect spi_clk offload/spi_clk + ad_connect spi_clk offload/ctrl_clk + ad_connect spi_clk execution/clk + ad_connect clk axi_regmap/s_axi_aclk + ad_connect spi_clk axi_regmap/spi_clk + ad_connect spi_clk interconnect/clk + + ad_connect axi_regmap/spi_resetn offload/spi_resetn + ad_connect axi_regmap/spi_resetn execution/resetn + ad_connect axi_regmap/spi_resetn interconnect/resetn + + ad_connect drdy offload/trigger + + ad_connect resetn axi_regmap/s_axi_aresetn + ad_connect irq axi_regmap/irq + + +current_bd_instance / + +ad_connect adc_data_ready spi_adc/drdy + +# dma for the ADC + +ad_ip_instance axi_dmac axi_cn0540_dma +ad_ip_parameter axi_cn0540_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_cn0540_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_cn0540_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_cn0540_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_cn0540_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_cn0540_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_cn0540_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_SRC 32 +ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_connect $sys_cpu_clk spi_adc/clk +ad_connect $sys_cpu_resetn spi_adc/resetn +ad_connect $sys_cpu_resetn axi_cn0540_dma/m_dest_axi_aresetn + +ad_connect spi_adc/m_spi adc_spi +ad_connect $sys_dma_clk spi_adc/spi_clk +ad_connect axi_cn0540_dma/s_axis spi_adc/M_AXIS_SAMPLE + +# AXI address definitions + +ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap +ad_cpu_interconnect 0x44a30000 axi_cn0540_dma +ad_cpu_interconnect 0x44a40000 axi_iic_cn0540 + +ad_connect $sys_dma_clk axi_cn0540_dma/s_axis_aclk + +# interrupts + +ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt +ad_cpu_interrupt "ps-11" "mb-11" spi_adc/irq + +# memory interconnects + +ad_mem_hp0_interconnect $sys_cpu_clk axi_cn0540_dma/m_dest_axi diff --git a/projects/cn0540/coraz7s/Makefile b/projects/cn0540/coraz7s/Makefile new file mode 100755 index 000000000..7f135302a --- /dev/null +++ b/projects/cn0540/coraz7s/Makefile @@ -0,0 +1,22 @@ +#################################################################################### +## Copyright 2019-2020(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := cn0540_coraz7s + +M_DEPS += ../common/cn0540_bd.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc +M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom + +include ../../scripts/project-xilinx.mk diff --git a/projects/cn0540/coraz7s/system_bd.tcl b/projects/cn0540/coraz7s/system_bd.tcl new file mode 100755 index 000000000..7711677d2 --- /dev/null +++ b/projects/cn0540/coraz7s/system_bd.tcl @@ -0,0 +1,14 @@ + +source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring + +set sys_dma_clk [get_bd_nets sys_dma_clk] + +source ../common/cn0540_bd.tcl + diff --git a/projects/cn0540/coraz7s/system_constr.xdc b/projects/cn0540/coraz7s/system_constr.xdc new file mode 100755 index 000000000..2876f55bc --- /dev/null +++ b/projects/cn0540/coraz7s/system_constr.xdc @@ -0,0 +1,25 @@ + +# SPI interface + +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports cn0540_spi_sclk] ; ## CK_IO13 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports cn0540_spi_miso] ; ## CK_IO12 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports cn0540_spi_mosi] ; ## CK_IO11 +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports cn0540_spi_cs] ; ## CK_IO10 + +# reset and GPIO signals + +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports cn0540_shutdown] ; ## CK_IO9 +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports cn0540_reset_adc] ; ## CK_IO7 +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports cn0540_csb_aux] ; ## CK_IO5 +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports cn0540_sw_ff] ; ## CK_IO4 +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy_aux] ; ## CK_IO3 +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports cn0540_blue_led] ; ## CK_IO1 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports cn0540_yellow_led] ; ## CK_IO0 + +# syncronization and timing + +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports cn0540_sync_in] ; ## CK_IO6 +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy] ; ## CK_IO2 + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports cn0540_scl] ; ## CK_SCL +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports cn0540_sda] ; ## CK_SDA diff --git a/projects/cn0540/coraz7s/system_project.tcl b/projects/cn0540/coraz7s/system_project.tcl new file mode 100755 index 000000000..a024fa5fa --- /dev/null +++ b/projects/cn0540/coraz7s/system_project.tcl @@ -0,0 +1,15 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project cn0540_coraz7s + +adi_project_files cn0540_coraz7s [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] + +#adi_project_run cn0540_coraz7s + diff --git a/projects/cn0540/coraz7s/system_top.v b/projects/cn0540/coraz7s/system_top.v new file mode 100755 index 000000000..460b2e6a6 --- /dev/null +++ b/projects/cn0540/coraz7s/system_top.v @@ -0,0 +1,184 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [1:0] btn, + inout [5:0] led, + + inout cn0540_scl, + inout cn0540_sda, + + inout cn0540_shutdown, + inout cn0540_reset_adc, + inout cn0540_csb_aux, + inout cn0540_sw_ff, + inout cn0540_drdy_aux, + inout cn0540_blue_led, + inout cn0540_yellow_led, + inout cn0540_sync_in, + + input cn0540_spi_miso, + output cn0540_spi_mosi, + output cn0540_spi_sclk, + output cn0540_spi_cs, + inout cn0540_drdy); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_buttons ( + .dio_t(gpio_t[1:0]), + .dio_i(gpio_o[1:0]), + .dio_o(gpio_i[1:0]), + .dio_p(btn)); + + ad_iobuf #( + .DATA_WIDTH(6) + ) i_iobuf_leds ( + .dio_t(gpio_t[7:2]), + .dio_i(gpio_o[7:2]), + .dio_o(gpio_i[7:2]), + .dio_p(led)); + + assign gpio_i[31:8] = gpio_o[31:8]; + + ad_iobuf #( + .DATA_WIDTH(9) + ) i_iobuf_cn0540_gpio ( + .dio_t(gpio_t[40:32]), + .dio_i(gpio_o[40:32]), + .dio_o(gpio_i[40:32]), + .dio_p({ + cn0540_shutdown, + cn0540_reset_adc, + cn0540_csb_aux, + cn0540_sw_ff, + cn0540_drdy_aux, + cn0540_blue_led, + cn0540_yellow_led, + cn0540_sync_in, + cn0540_drdy})); + + assign gpio_i[63:41] = gpio_o[63:41]; + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .adc_spi_sdo (cn0540_spi_mosi), + .adc_spi_sdo_t (), + .adc_spi_sdi (cn0540_spi_miso), + .adc_spi_cs (cn0540_spi_cs), + .adc_spi_sclk (cn0540_spi_sclk), + .adc_data_ready (cn0540_drdy), + .iic_cn0540_scl_io (cn0540_scl), + .iic_cn0540_sda_io (cn0540_sda), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o()); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/common/coraz7s/coraz7s_system_bd.tcl b/projects/common/coraz7s/coraz7s_system_bd.tcl index 351b80299..2d9c2cc0e 100644 --- a/projects/common/coraz7s/coraz7s_system_bd.tcl +++ b/projects/common/coraz7s/coraz7s_system_bd.tcl @@ -37,7 +37,7 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 -ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 40.0 ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64 @@ -52,34 +52,34 @@ ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 ad_ip_instance proc_sys_reset sys_rstgen ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 -ad_ip_instance proc_sys_reset sys_200m_rstgen -ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1 +ad_ip_instance proc_sys_reset sys_dma_rstgen +ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1 # system reset/clock definitions ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 -ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_dma_clk sys_ps7/FCLK_CLK1 ad_connect sys_cpu_reset sys_rstgen/peripheral_reset ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N -ad_connect sys_200m_reset sys_200m_rstgen/peripheral_reset -ad_connect sys_200m_resetn sys_200m_rstgen/peripheral_aresetn -ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk -ad_connect sys_200m_rstgen/ext_reset_in sys_ps7/FCLK_RESET1_N +ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset +ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn +ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk +ad_connect sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET1_N # generic system clocks pointers set sys_cpu_clk [get_bd_nets sys_cpu_clk] -set sys_dma_clk [get_bd_nets sys_200m_clk] -set sys_iodelay_clk [get_bd_nets sys_200m_clk] +set sys_dma_clk [get_bd_nets sys_dma_clk] +set sys_iodelay_clk [get_bd_nets sys_dma_clk] set sys_cpu_reset [get_bd_nets sys_cpu_reset] set sys_cpu_resetn [get_bd_nets sys_cpu_resetn] -set sys_dma_reset [get_bd_nets sys_200m_reset] -set sys_dma_resetn [get_bd_nets sys_200m_resetn] -set sys_iodelay_reset [get_bd_nets sys_200m_reset] -set sys_iodelay_resetn [get_bd_nets sys_200m_resetn] +set sys_dma_reset [get_bd_nets sys_dma_reset] +set sys_dma_resetn [get_bd_nets sys_dma_resetn] +set sys_iodelay_reset [get_bd_nets sys_dma_reset] +set sys_iodelay_resetn [get_bd_nets sys_dma_resetn] # interface connections @@ -143,3 +143,6 @@ ad_connect sys_concat_intc/In0 GND # interconnects and address mapping ad_cpu_interconnect 0x45000000 axi_sysid_0 + +ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +