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ad9361- dac data path split

main
Rejeesh Kutty 2016-09-23 16:13:46 -04:00
parent 6735333aea
commit 1a11e28821
3 changed files with 203 additions and 239 deletions
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7
library/axi_ad9361/axi_ad9361.v
View File

@ -654,8 +654,11 @@ module axi_ad9361 (
axi_ad9361_tx #(
.ID (ID),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE),
.R1_MODE_EN (R1_MODE_EN))
.MODE_1R1T (R1_MODE_EN),
.DDS_DISABLE (DAC_DATAPATH_DISABLE),
.USERPORTS_DISABLE (DAC_DATAPATH_DISABLE),
.DELAYCNTRL_DISABLE (DAC_DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.dac_clk (clk),
.dac_valid (dac_valid_s),

260
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -37,142 +37,95 @@
`timescale 1ns/100ps
module axi_ad9361_tx (
// dac interface
dac_clk,
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
adc_data,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
// master/slave
dac_sync_in,
dac_sync_out,
// dma interface
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
// gpio
up_dac_gpio_in,
up_dac_gpio_out,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
module axi_ad9361_tx #(
// parameters
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
parameter R1_MODE_EN = 0;
parameter ID = 0,
parameter MODE_1R1T = 0,
parameter DDS_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter DELAYCNTRL_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// dac interface
input dac_clk;
output dac_valid;
output [47:0] dac_data;
output dac_clksel;
output dac_r1_mode;
input [47:0] adc_data;
input dac_clk,
output dac_valid,
output [47:0] dac_data,
output dac_clksel,
output dac_r1_mode,
input [47:0] adc_data,
// delay interface
output [15:0] up_dld;
output [79:0] up_dwdata;
input [79:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
output [15:0] up_dld,
output [79:0] up_dwdata,
input [79:0] up_drdata,
input delay_clk,
output delay_rst,
input delay_locked,
// master/slave
input dac_sync_in;
output dac_sync_out;
input dac_sync_in,
output dac_sync_out,
// dma interface
output dac_enable_i0;
output dac_valid_i0;
input [15:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [15:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [15:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [15:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
output dac_enable_i0,
output dac_valid_i0,
input [15:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [15:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [15:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [15:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// gpio
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out,
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// configuration settings
localparam CONFIG = (DDS_DISABLE * 64) +
(DELAYCNTRL_DISABLE * 32) +
(MODE_1R1T * 16) +
(USERPORTS_DISABLE * 8) +
(IQCORRECTION_DISABLE * 1);
// internal registers
reg dac_data_sync = 'd0;
reg [ 7:0] dac_rate_cnt = 'd0;
reg dac_valid = 'd0;
reg dac_valid_i0 = 'd0;
reg dac_valid_q0 = 'd0;
reg dac_valid_i1 = 'd0;
reg dac_valid_q1 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
reg dac_valid_int = 'd0;
reg dac_valid_i0_int = 'd0;
reg dac_valid_q0_int = 'd0;
reg dac_valid_i1_int = 'd0;
reg dac_valid_q1_int = 'd0;
reg up_wack_int = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
// internal clock and resets
@ -184,9 +137,9 @@ module axi_ad9361_tx (
wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s;
wire [47:0] dac_data_int_s;
wire [ 5:0] up_wack_s;
wire [ 5:0] up_rack_s;
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
// master/slave
@ -208,28 +161,36 @@ module axi_ad9361_tx (
// dma interface
assign dac_valid = dac_valid_int;
assign dac_valid_i0 = dac_valid_i0_int;
assign dac_valid_q0 = dac_valid_q0_int;
assign dac_valid_i1 = dac_valid_i1_int;
assign dac_valid_q1 = dac_valid_q1_int;
always @(posedge dac_clk) begin
dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
dac_valid_i0 <= dac_valid;
dac_valid_q0 <= dac_valid;
dac_valid_i1 <= dac_valid & ~dac_r1_mode;
dac_valid_q1 <= dac_valid & ~dac_r1_mode;
dac_valid_int <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
dac_valid_i0_int <= dac_valid_int;
dac_valid_q0_int <= dac_valid_int;
dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode;
dac_valid_q1_int <= dac_valid_int & ~dac_r1_mode;
end
// processor read interface
assign up_wack = up_wack_int;
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
up_wack_int <= 'd0;
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
up_wack_int <= | up_wack_s;
up_rack_int <= | up_rack_s;
up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
end
end
@ -238,11 +199,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (0),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_i0),
.adc_data (adc_data[11:0]),
.dac_data (dac_data[11:0]),
@ -267,11 +231,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (0),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_q0),
.adc_data (adc_data[23:12]),
.dac_data (dac_data[23:12]),
@ -291,19 +258,19 @@ module axi_ad9361_tx (
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
generate
if (R1_MODE_EN == 0) begin
// dac channel
axi_ad9361_tx_channel #(
.CHANNEL_ID (2),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (MODE_1R1T),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_i1),
.adc_data (adc_data[35:24]),
.dac_data (dac_data[35:24]),
@ -328,11 +295,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (3),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (MODE_1R1T),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_q1),
.adc_data (adc_data[47:36]),
.dac_data (dac_data[47:36]),
@ -352,12 +322,14 @@ module axi_ad9361_tx (
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
end
endgenerate
// dac common processor interface
up_dac_common #(.ID (ID)) i_up_dac_common (
up_dac_common #(
.ID (ID),
.CONFIG (CONFIG),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE))
i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -397,7 +369,11 @@ module axi_ad9361_tx (
// dac delay control
up_delay_cntrl #(.DATA_WIDTH(16), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
up_delay_cntrl #(
.DISABLE (DELAYCNTRL_DISABLE),
.DATA_WIDTH(16),
.BASE_ADDRESS(6'h12))
i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

175
library/axi_ad9361/axi_ad9361_tx_channel.v
View File

@ -37,85 +37,61 @@
`timescale 1ns/100ps
module axi_ad9361_tx_channel (
// dac interface
dac_clk,
dac_rst,
dac_valid,
dma_data,
adc_data,
dac_data,
dac_data_out,
dac_data_in,
// processor interface
dac_enable,
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
module axi_ad9361_tx_channel #(
// parameters
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 32'h0,
parameter DISABLE = 0,
parameter DDS_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// dac interface
input dac_clk,
input dac_rst,
input dac_valid,
input [15:0] dma_data,
input [11:0] adc_data,
output [11:0] dac_data,
output [11:0] dac_data_out,
input [11:0] dac_data_in,
// processor interface
output dac_enable,
input dac_data_sync,
input dac_dds_format,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter Q_OR_I_N = 0;
parameter DATAPATH_DISABLE = 0;
localparam PRBS_SEL = CHANNEL_ID;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
localparam PRBS_P15 = 2;
localparam PRBS_P20 = 3;
// dac interface
input dac_clk;
input dac_rst;
input dac_valid;
input [15:0] dma_data;
input [11:0] adc_data;
output [11:0] dac_data;
output [11:0] dac_data_out;
input [11:0] dac_data_in;
// processor interface
output dac_enable;
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_valid_sel = 'd0;
reg dac_enable = 'd0;
reg [11:0] dac_data = 'd0;
reg [11:0] dac_data_out = 'd0;
reg dac_enable_int = 'd0;
reg [11:0] dac_data_int = 'd0;
reg [11:0] dac_data_out_int = 'd0;
reg [23:0] dac_pn_seq = 'd0;
reg [11:0] dac_pn_data = 'd0;
reg [15:0] dac_pat_data = 'd0;
@ -142,6 +118,9 @@ module axi_ad9361_tx_channel (
wire dac_iqcor_enb_s;
wire [15:0] dac_iqcor_coeff_1_s;
wire [15:0] dac_iqcor_coeff_2_s;
wire up_wack_s;
wire up_rack_s;
wire [31:0] up_rdata_s;
// standard prbs functions
@ -271,41 +250,42 @@ module axi_ad9361_tx_channel (
// dac iq correction
assign dac_enable = (DISABLE == 1) ? 'd0 : dac_enable_int;
assign dac_data = (DISABLE == 1) ? 'd0 : dac_data_int;
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
if (dac_iqcor_valid_s == 1'b1) begin
dac_data <= dac_iqcor_data_s[15:4];
dac_data_int <= dac_iqcor_data_s[15:4];
end
end
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_iqcor_valid_s = dac_valid;
assign dac_iqcor_data_s = {dac_data_out, 4'd0};
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE))
i_ad_iqcor (
.clk (dac_clk),
.valid (dac_valid),
.data_in ({dac_data_out, 4'd0}),
.data_in ({dac_data_out_int, 4'd0}),
.data_iq ({dac_data_in, 4'd0}),
.valid_out (dac_iqcor_valid_s),
.data_out (dac_iqcor_data_s),
.iqcor_enable (dac_iqcor_enb_s),
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
end
endgenerate
// dac mux
assign dac_data_out = (DISABLE == 1) ? 'd0 : dac_data_out_int;
always @(posedge dac_clk) begin
case (dac_data_sel_s)
4'h9: dac_data_out <= dac_pn_data;
4'h8: dac_data_out <= adc_data;
4'h3: dac_data_out <= 12'd0;
4'h2: dac_data_out <= dma_data[15:4];
4'h1: dac_data_out <= dac_pat_data[15:4];
default: dac_data_out <= dac_dds_data[15:4];
4'h9: dac_data_out_int <= dac_pn_data;
4'h8: dac_data_out_int <= adc_data;
4'h3: dac_data_out_int <= 12'd0;
4'h2: dac_data_out_int <= dma_data[15:4];
4'h1: dac_data_out_int <= dac_pat_data[15:4];
default: dac_data_out_int <= dac_dds_data[15:4];
endcase
end
@ -358,11 +338,9 @@ module axi_ad9361_tx_channel (
// dds
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_s = 16'd0;
end else begin
ad_dds i_dds (
ad_dds #(
.DISABLE (DDS_DISABLE))
i_dds (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0),
@ -370,12 +348,19 @@ module axi_ad9361_tx_channel (
.dds_phase_1 (dac_dds_phase_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s));
end
endgenerate
// single channel processor
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
assign up_wack = (DISABLE == 1) ? 'd0 : up_wack_s;
assign up_rack = (DISABLE == 1) ? 'd0 : up_rack_s;
assign up_rdata = (DISABLE == 1) ? 'd0 : up_rdata_s;
up_dac_channel #(
.CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -410,11 +395,11 @@ module axi_ad9361_tx_channel (
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule