jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP
Laszlo Nagy
Laszlo Nagy
parent
56a25afa68
commit
1a9e7dbeb4
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := jesd204_versal_gt_adapter_rx
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GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v
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XILINX_DEPS += ../jesd204_common/sync_header_align.v
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XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl
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include ../../scripts/library.mk
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@ -0,0 +1,98 @@
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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
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// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_versal_gt_adapter_rx (
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input [127 : 0] rxdata,
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input [5 : 0] rxheader,
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output rxgearboxslip,
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input [1 : 0] rxheadervalid,
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// Interface to Link layer core
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output [63:0] rx_data,
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output [1:0] rx_header,
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output rx_block_sync,
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input usr_clk
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);
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// Sync header alignment
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wire rx_bitslip_req_s;
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reg [4:0] rx_bitslip_done_cnt = 'h0;
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always @(posedge usr_clk) begin
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if (rx_bitslip_done_cnt[4]) begin
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rx_bitslip_done_cnt <= 'b0;
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end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[4]) begin
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rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
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end
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end
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reg rx_bitslip_req_s_d = 1'b0;
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always @(posedge usr_clk) begin
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rx_bitslip_req_s_d <= rx_bitslip_req_s;
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end
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assign rxgearboxslip = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
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wire [63:0] rxdata_flip;
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genvar i;
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for (i = 0; i < 64; i=i+1) begin
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assign rxdata_flip[63-i] = rxdata[i];
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end
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// Sync header alignment
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sync_header_align i_sync_header_align (
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.clk(usr_clk),
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.reset(~rxheadervalid[0]),
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// Flip header bits and data
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.i_data({rxheader[0],rxheader[1],rxdata_flip[63:0]}),
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.i_slip(rx_bitslip_req_s),
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.i_slip_done(rx_bitslip_done_cnt[4]),
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.o_data(rx_data),
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.o_header(rx_header),
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.o_block_sync(rx_block_sync)
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);
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endmodule
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@ -0,0 +1,68 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
|
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# more information. This commercial license is sub-licensable (if you purchase
|
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# chips from Analog Devices, incorporate them into your PCB level product, and
|
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# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
|
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# or publication in which you use this JESD204 HDL core. (You are not required
|
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# to do so; it is up to your common sense to decide whether you want to comply
|
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create jesd204_versal_gt_adapter_rx
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adi_ip_files jesd204_versal_gt_adapter_rx [list \
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jesd204_versal_gt_adapter_rx.v \
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../jesd204_common/sync_header_align.v \
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]
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adi_ip_properties_lite jesd204_versal_gt_adapter_rx
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set_property display_name "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core]
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set_property description "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core]
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adi_add_bus "RX" "master" \
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"xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \
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"xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \
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{ \
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{ "rx_data" "rxdata" } \
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{ "rx_header" "rxheader" } \
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{ "rx_block_sync" "rxblock_sync" } \
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}
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ipx::save_core [ipx::current_core]
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@ -0,0 +1,13 @@
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := jesd204_versal_gt_adapter_tx
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GENERIC_DEPS += jesd204_versal_gt_adapter_tx.v
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XILINX_DEPS += jesd204_versal_gt_adapter_tx_ip.tcl
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include ../../scripts/library.mk
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@ -0,0 +1,68 @@
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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
|
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// Please read this, and understand the freedoms and responsibilities you have
|
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// by using this source code/core.
|
||||
//
|
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
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//
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// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
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// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
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// License version 2 as published by the Free Software Foundation.
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//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
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// along with this source code, and binary. If not, see
|
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
|
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
|
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// purchase a JESD204 license, end users of your product will also have a
|
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_versal_gt_adapter_tx (
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output [127 : 0] txdata,
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output [5 : 0] txheader,
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// Interface to Link layer core
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input [63:0] tx_data,
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input [1:0] tx_header,
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input usr_clk
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);
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wire [63:0] tx_data_flip;
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genvar i;
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for (i = 0; i < 64; i=i+1) begin
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assign tx_data_flip[63-i] = tx_data[i];
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end
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assign txdata = {64'b0,tx_data_flip};
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// Flip header bits and data
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assign txheader = {4'b0,tx_header[0],tx_header[1]};
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endmodule
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@ -0,0 +1,66 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
|
||||
#
|
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
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#
|
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# This core is free software, you can use run, copy, study, change, ask
|
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# questions about and improve this core. Distribution of source, or resulting
|
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# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
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# License version 2 as published by the Free Software Foundation.
|
||||
#
|
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
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# <http://www.gnu.org/licenses/>.
|
||||
#
|
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# Commercial licenses (with commercial support) of this JESD204 core are also
|
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# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create jesd204_versal_gt_adapter_tx
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adi_ip_files jesd204_versal_gt_adapter_tx [list \
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jesd204_versal_gt_adapter_tx.v
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]
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adi_ip_properties_lite jesd204_versal_gt_adapter_tx
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set_property display_name "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
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set_property description "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
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adi_add_bus "TX" "slave" \
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"xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
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"xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
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{ \
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{ "tx_data" "txdata" } \
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{ "tx_header" "txheader" } \
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}
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ipx::save_core [ipx::current_core]
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