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Motcon2 initial commit

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Adrian Costina 2015-02-20 16:15:01 +02:00
parent cf456caa0e
commit 1b19a1b78a
4 changed files with 1403 additions and 0 deletions
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projects/motcon2_fmc/common/motcon2_fmc_bd.tcl Normal file
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# motor control
# port definition
# gpio
set_property LEFT 34 [get_bd_ports GPIO_I]
set_property LEFT 34 [get_bd_ports GPIO_O]
set_property LEFT 34 [get_bd_ports GPIO_T]
# position detection interface
set position_m1_i [ create_bd_port -dir I -from 2 -to 0 position_m1_i ]
set position_m2_i [ create_bd_port -dir I -from 2 -to 0 position_m2_i ]
# current monitor interface
# clock
set adc_clk_o [ create_bd_port -dir O adc_clk_o ]
# data motor 1
set adc_m1_ia_dat_i [ create_bd_port -dir I adc_m1_ia_dat_i ]
set adc_m1_ib_dat_i [ create_bd_port -dir I adc_m1_ib_dat_i ]
set adc_m1_vbus_dat_i [ create_bd_port -dir I adc_m1_vbus_dat_i ]
# data motor 2
set adc_m2_ia_dat_i [ create_bd_port -dir I adc_m2_ia_dat_i ]
set adc_m2_ib_dat_i [ create_bd_port -dir I adc_m2_ib_dat_i ]
set adc_m2_vbus_dat_i [ create_bd_port -dir I adc_m2_vbus_dat_i ]
# motor control interface
set gpo_o [ create_bd_port -dir o -from 3 -to 0 gpo_o]
# motor 1
set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o]
set pwm_m1_al_o [ create_bd_port -dir O pwm_m1_al_o]
set pwm_m1_ah_o [ create_bd_port -dir O pwm_m1_ah_o]
set pwm_m1_cl_o [ create_bd_port -dir O pwm_m1_cl_o]
set pwm_m1_ch_o [ create_bd_port -dir O pwm_m1_ch_o]
set pwm_m1_bl_o [ create_bd_port -dir O pwm_m1_bl_o]
set pwm_m1_bh_o [ create_bd_port -dir O pwm_m1_bh_o]
# motor 2
set fmc_m2_en_o [ create_bd_port -dir O fmc_m2_en_o]
set pwm_m2_al_o [ create_bd_port -dir O pwm_m2_al_o]
set pwm_m2_ah_o [ create_bd_port -dir O pwm_m2_ah_o]
set pwm_m2_cl_o [ create_bd_port -dir O pwm_m2_cl_o]
set pwm_m2_ch_o [ create_bd_port -dir O pwm_m2_ch_o]
set pwm_m2_bl_o [ create_bd_port -dir O pwm_m2_bl_o]
set pwm_m2_bh_o [ create_bd_port -dir O pwm_m2_bh_o]
# interrupts
set motcon2_c_m1_intr [create_bd_port -dir O motcon2_c_m1_intr]
set motcon2_c_m2_intr [create_bd_port -dir O motcon2_c_m2_intr]
set motcon2_s_d1_intr [create_bd_port -dir O motcon2_s_d1_intr]
set motcon2_s_d2_intr [create_bd_port -dir O motcon2_s_d2_intr]
set motcon2_ctrl_m1_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m1_intr ]
set motcon2_ctrl_m2_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m2_intr ]
# Ethernet
# phy 1
set eth1_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii ]
# phy 2
set eth2_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii ]
#common mdio interface
set eth_mdio_mdc [ create_bd_port -dir O eth_mdio_mdc ]
set eth_mdio_o [ create_bd_port -dir O eth_mdio_o ]
set eth_mdio_t [ create_bd_port -dir O eth_mdio_t ]
set eth_mdio_i [ create_bd_port -dir I eth_mdio_i ]
#common reset
set eth_phy_rst_n [ create_bd_port -dir O eth_phy_rst_n ]
# reference clock for the delay interface used for the gmii to rgmii conversion
set refclk [ create_bd_port -dir o -type clk refclk ]
set refclk_rst [ create_bd_port -dir o -from 0 -to 0 -type rst refclk_rst ]
# iic
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ee2
set iic_ee2_intr [create_bd_port -dir O iic_ee2_intr]
# spi
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_csn_o [create_bd_port -dir O spi_csn_o]
set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
set spi_miso_i [create_bd_port -dir I spi_miso_i]
# xadc interface
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
#create_bd_port -dir O -from 4 -to 0 muxaddr_out
# core instantiation and configuration
# additions to default configuration
# increase cpu interconnect to accomodate new cores
set_property -dict [list CONFIG.NUM_MI {21}] $axi_cpu_interconnect
# Enable additional peripherals from the PS7 block
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {EMIO} ] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
# Add additional clocks to be used by gmii to rgmii modules and current monitoring modules
set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen
# speed detectors
# speed detector core motor 1
set speed_detector_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m1 ]
# dma motor 1
set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m1_dma
# speed detector core motor 2
set speed_detector_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m2 ]
# dma motor 2
set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m2_dma
# current monitor peripherals
# current monitor core motor 1
set current_monitor_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m1 ]
# dma motor 1
set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ]
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m1_dma
# data packer motor 1
#
set current_monitor_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m1_apack]
set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m1_apack
# set current_monitor_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m1_pack ]
# set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m1_pack
# set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m1_pack
# current monitor core motor 2
set current_monitor_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m2 ]
# dma motor 2
set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ]
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m2_dma
# data packer motor 2
set current_monitor_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m2_apack]
set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m2_apack
#set current_monitor_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m2_pack ]
#set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m2_pack
#set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m2_pack
#controller
# controller core motor 1
set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ]
# dma motor 1
set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ]
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma
# data packer motor 1
set controller_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m1_apack]
set_property -dict [list CONFIG.CHANNELS {8}] $controller_m1_apack
set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m1_apack
#set controller_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m1_pack ]
#set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m1_pack
#set_property -dict [ list CONFIG.CH_DW {32} ] $controller_m1_pack
# controller core motor 2
set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ]
# dma motor 2
set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ]
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma
# data packer motor 2
#set controller_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m2_pack ]
#set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m2_pack
set controller_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m2_apack]
set_property -dict [list CONFIG.CHANNELS {8}] $controller_m2_apack
set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m2_apack
#ethernet gmii to rgmii converters
# phy 1
set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ]
set_property -dict [list CONFIG.PHY_AD {"00000"}] [get_bd_cells gmii_to_rgmii_eth1]
# phy 2
set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ]
set_property -dict [list CONFIG.PHY_AD {"00001"}] [get_bd_cells gmii_to_rgmii_eth2]
# iic
set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ]
# xadc
#set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ]
#set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core
#set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core
#set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core
#set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core
#set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core
#set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core
#set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core
# additional interconnect
set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ]
set_property -dict [ list CONFIG.NUM_SI {6} CONFIG.NUM_MI {1} ] $axi_mem_interconnect
# connections
# speed detector
# motor 1
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1_dma/m_dest_axi_aresetn]
connect_bd_net -net position_m1_i_1 [get_bd_ports position_m1_i] [get_bd_pins speed_detector_m1/position_i]
connect_bd_net -net speed_detector_adc_new_speed_m1 [get_bd_pins speed_detector_m1/new_speed_o] [get_bd_pins speed_detector_m1_dma/fifo_wr_en]
connect_bd_net -net speed_detector_adc_speed_m1 [get_bd_pins speed_detector_m1/speed_o] [get_bd_pins speed_detector_m1_dma/fifo_wr_din]
# motor 2
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2_dma/m_dest_axi_aresetn]
connect_bd_net -net position_m2_i_1 [get_bd_ports position_m2_i] [get_bd_pins speed_detector_m2/position_i]
connect_bd_net -net speed_detector_adc_new_speed_m2 [get_bd_pins speed_detector_m2/new_speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_en]
connect_bd_net -net speed_detector_adc_speed_m2 [get_bd_pins speed_detector_m2/speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_din]
# interrupt
connect_bd_net -net speed_detector_m1_dma_intr [get_bd_pins speed_detector_m1_dma/irq] [get_bd_ports motcon2_s_d1_intr]
connect_bd_net -net speed_detector_m2_dma_intr [get_bd_pins speed_detector_m2_dma/irq] [get_bd_ports motcon2_s_d2_intr]
# current monitor
connect_bd_net -net current_monitor_m1_adc_clk_o [get_bd_ports adc_clk_o] [get_bd_pins current_monitor_m1/adc_clk_o]
# motor 1
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i]
connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i]
connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i]
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_apack/chan_enable_0]
connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_apack/chan_enable_1]
connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_apack/chan_enable_2]
connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_apack/chan_enable_3]
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_0] [get_bd_pins current_monitor_m1/i_ready_o]
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_1] [get_bd_pins current_monitor_m1/i_ready_o]
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_2] [get_bd_pins current_monitor_m1/i_ready_o]
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_3] [get_bd_pins current_monitor_m1/i_ready_o]
connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_apack/chan_data_0]
connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_apack/chan_data_1]
connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_apack/chan_data_2]
connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_apack/chan_data_3]
connect_bd_net [get_bd_pins current_monitor_m1_apack/ddata] [get_bd_pins current_monitor_m1_dma/fifo_wr_din]
connect_bd_net [get_bd_pins current_monitor_m1_apack/dvalid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en]
# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0]
# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
# connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_pack/adc_enable_0]
# connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_pack/adc_enable_1]
# connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_pack/adc_enable_2]
# connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_pack/adc_enable_3]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_0] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_1] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_2] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_3] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_pack/adc_data_0]
# connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_pack/adc_data_1]
# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_2]
# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_3]
# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_data] [get_bd_pins current_monitor_m1_dma/fifo_wr_din]
# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_valid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en]
# motor 2
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i]
connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i]
connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i]
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_apack/chan_enable_0]
connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_apack/chan_enable_1]
connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_apack/chan_enable_2]
connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_apack/chan_enable_3]
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_0] [get_bd_pins current_monitor_m2/i_ready_o]
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_1] [get_bd_pins current_monitor_m2/i_ready_o]
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_2] [get_bd_pins current_monitor_m2/i_ready_o]
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_3] [get_bd_pins current_monitor_m2/i_ready_o]
connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_apack/chan_data_0]
connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_apack/chan_data_1]
connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_apack/chan_data_2]
connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_apack/chan_data_3]
connect_bd_net [get_bd_pins current_monitor_m2_apack/ddata] [get_bd_pins current_monitor_m2_dma/fifo_wr_din]
connect_bd_net [get_bd_pins current_monitor_m2_apack/dvalid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en]
# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0]
# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
# connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_pack/adc_enable_0]
# connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_pack/adc_enable_1]
# connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_pack/adc_enable_2]
# connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_pack/adc_enable_3]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_0] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_1] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_2] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_3] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_pack/adc_data_0]
# connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_pack/adc_data_1]
# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_2]
# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_3]
# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_valid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en]
# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_data] [get_bd_pins current_monitor_m2_dma/fifo_wr_din]
# interrupts
connect_bd_net -net axi_current_monitor_1_dma_intr [get_bd_pins current_monitor_m1_dma/irq] [get_bd_ports motcon2_c_m1_intr]
connect_bd_net -net axi_current_monitor_2_dma_intr [get_bd_pins current_monitor_m2_dma/irq] [get_bd_ports motcon2_c_m2_intr]
#controller
# motor 1
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1_dma/m_dest_axi_aresetn]
connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins controller_m1/fmc_m1_en_o]
connect_bd_net -net axi_mc_controller_m1_pwm_al_o [get_bd_ports pwm_m1_al_o] [get_bd_pins controller_m1/pwm_al_o]
connect_bd_net -net axi_mc_controller_m1_pwm_ah_o [get_bd_ports pwm_m1_ah_o] [get_bd_pins controller_m1/pwm_ah_o]
connect_bd_net -net axi_mc_controller_m1_pwm_bl_o [get_bd_ports pwm_m1_bl_o] [get_bd_pins controller_m1/pwm_bl_o]
connect_bd_net -net axi_mc_controller_m1_pwm_bh_o [get_bd_ports pwm_m1_bh_o] [get_bd_pins controller_m1/pwm_bh_o]
connect_bd_net -net axi_mc_controller_m1_pwm_cl_o [get_bd_ports pwm_m1_cl_o] [get_bd_pins controller_m1/pwm_cl_o]
connect_bd_net -net axi_mc_controller_m1_pwm_ch_o [get_bd_ports pwm_m1_ch_o] [get_bd_pins controller_m1/pwm_ch_o]
connect_bd_net -net axi_mc_controller_m1_sensors_o [get_bd_pins controller_m1/sensors_o] [get_bd_pins speed_detector_m1/hall_bemf_i]
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins controller_m1/position_i] [get_bd_pins speed_detector_m1/position_o]
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins controller_m1/ctrl_data_valid_i] [get_bd_pins current_monitor_m1/i_ready_o]
#connect_bd_net -net controller_m1_adc_clk_o [get_bd_pins controller_m1_pack/adc_clk] [get_bd_pins controller_m1/adc_clk_o]
#connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
#connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_pack/adc_enable_0]
#connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_pack/adc_enable_1]
#connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_pack/adc_enable_2]
#connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_pack/adc_enable_3]
#connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_pack/adc_enable_4]
#connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_pack/adc_enable_5]
#connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_pack/adc_enable_6]
#connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_pack/adc_enable_7]
#connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_pack/adc_valid_0]
#connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_pack/adc_valid_1]
#connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_pack/adc_valid_2]
#connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_pack/adc_valid_3]
#connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_pack/adc_valid_4]
#connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_pack/adc_valid_5]
#connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_pack/adc_valid_6]
#connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_pack/adc_valid_7]
#connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_pack/adc_data_0]
#connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_pack/adc_data_1]
#connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_pack/adc_data_2]
#connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_pack/adc_data_3]
#connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_pack/adc_data_4]
#connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_pack/adc_data_5]
#connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_pack/adc_data_6]
#connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_pack/adc_data_7]
#connect_bd_net [get_bd_pins controller_m1_pack/adc_data] [get_bd_pins controller_m1_dma/fifo_wr_din]
#connect_bd_net [get_bd_pins controller_m1_pack/adc_valid] [get_bd_pins controller_m1_dma/fifo_wr_en]
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins controller_m1_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_apack/chan_enable_0]
connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_apack/chan_enable_1]
connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_apack/chan_enable_2]
connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_apack/chan_enable_3]
connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_apack/chan_enable_4]
connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_apack/chan_enable_5]
connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_apack/chan_enable_6]
connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_apack/chan_enable_7]
connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_apack/chan_valid_0]
connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_apack/chan_valid_1]
connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_apack/chan_valid_2]
connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_apack/chan_valid_3]
connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_apack/chan_valid_4]
connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_apack/chan_valid_5]
connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_apack/chan_valid_6]
connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_apack/chan_valid_7]
connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_apack/chan_data_0]
connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_apack/chan_data_1]
connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_apack/chan_data_2]
connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_apack/chan_data_3]
connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_apack/chan_data_4]
connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_apack/chan_data_5]
connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_apack/chan_data_6]
connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_apack/chan_data_7]
connect_bd_net [get_bd_pins controller_m1_apack/ddata] [get_bd_pins controller_m1_dma/fifo_wr_din]
connect_bd_net [get_bd_pins controller_m1_apack/dvalid] [get_bd_pins controller_m1_dma/fifo_wr_en]
# motor 2
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2_dma/m_dest_axi_aresetn]
connect_bd_net -net axi_mc_controller_m2_fmc_m1_en_o [get_bd_ports fmc_m2_en_o] [get_bd_pins controller_m2/fmc_m1_en_o]
connect_bd_net -net axi_mc_controller_m2_pwm_al_o [get_bd_ports pwm_m2_al_o] [get_bd_pins controller_m2/pwm_al_o]
connect_bd_net -net axi_mc_controller_m2_pwm_ah_o [get_bd_ports pwm_m2_ah_o] [get_bd_pins controller_m2/pwm_ah_o]
connect_bd_net -net axi_mc_controller_m2_pwm_bl_o [get_bd_ports pwm_m2_bl_o] [get_bd_pins controller_m2/pwm_bl_o]
connect_bd_net -net axi_mc_controller_m2_pwm_bh_o [get_bd_ports pwm_m2_bh_o] [get_bd_pins controller_m2/pwm_bh_o]
connect_bd_net -net axi_mc_controller_m2_pwm_cl_o [get_bd_ports pwm_m2_cl_o] [get_bd_pins controller_m2/pwm_cl_o]
connect_bd_net -net axi_mc_controller_m2_pwm_ch_o [get_bd_ports pwm_m2_ch_o] [get_bd_pins controller_m2/pwm_ch_o]
connect_bd_net -net axi_mc_controller_m2_sensors_o [get_bd_pins controller_m2/sensors_o] [get_bd_pins speed_detector_m2/hall_bemf_i]
connect_bd_net -net axi_mc_speed_2_position_o [get_bd_pins controller_m2/position_i] [get_bd_pins speed_detector_m2/position_o]
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins controller_m2/ctrl_data_valid_i] [get_bd_pins current_monitor_m2/i_ready_o]
#connect_bd_net -net controller_m2_adc_clk_o [get_bd_pins controller_m2_pack/adc_clk] [get_bd_pins controller_m2/adc_clk_o]
#connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
#connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_pack/adc_enable_0]
#connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_pack/adc_enable_1]
#connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_pack/adc_enable_2]
#connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_pack/adc_enable_3]
#connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_pack/adc_enable_4]
#connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_pack/adc_enable_5]
#connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_pack/adc_enable_6]
#connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_pack/adc_enable_7]
#connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_pack/adc_valid_0]
#connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_pack/adc_valid_1]
#connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_pack/adc_valid_2]
#connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_pack/adc_valid_3]
#connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_pack/adc_valid_4]
#connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_pack/adc_valid_5]
#connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_pack/adc_valid_6]
#connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_pack/adc_valid_7]
#connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_pack/adc_data_0]
#connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_pack/adc_data_1]
#connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_pack/adc_data_2]
#connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_pack/adc_data_3]
#connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_pack/adc_data_4]
#connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_pack/adc_data_5]
#connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_pack/adc_data_6]
#connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_pack/adc_data_7]
#connect_bd_net [get_bd_pins controller_m2_pack/adc_data] [get_bd_pins controller_m2_dma/fifo_wr_din]
#connect_bd_net [get_bd_pins controller_m2_pack/adc_valid] [get_bd_pins controller_m2_dma/fifo_wr_en]
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins controller_m2_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_apack/chan_enable_0]
connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_apack/chan_enable_1]
connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_apack/chan_enable_2]
connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_apack/chan_enable_3]
connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_apack/chan_enable_4]
connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_apack/chan_enable_5]
connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_apack/chan_enable_6]
connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_apack/chan_enable_7]
connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_apack/chan_valid_0]
connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_apack/chan_valid_1]
connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_apack/chan_valid_2]
connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_apack/chan_valid_3]
connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_apack/chan_valid_4]
connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_apack/chan_valid_5]
connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_apack/chan_valid_6]
connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_apack/chan_valid_7]
connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_apack/chan_data_0]
connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_apack/chan_data_1]
connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_apack/chan_data_2]
connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_apack/chan_data_3]
connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_apack/chan_data_4]
connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_apack/chan_data_5]
connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_apack/chan_data_6]
connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_apack/chan_data_7]
connect_bd_net [get_bd_pins controller_m2_apack/ddata] [get_bd_pins controller_m2_dma/fifo_wr_din]
connect_bd_net [get_bd_pins controller_m2_apack/dvalid] [get_bd_pins controller_m2_dma/fifo_wr_en]
# interrupts
connect_bd_net -net controller_m1_dma_intr [get_bd_pins controller_m1_dma/irq] [get_bd_ports motcon2_ctrl_m1_intr]
connect_bd_net -net controller_m2_dma_intr [get_bd_pins controller_m2_dma/irq] [get_bd_ports motcon2_ctrl_m2_intr]
# ethernet
connect_bd_net -net sys_200m_clk [get_bd_ports refclk] [get_bd_pins sys_ps7/FCLK_CLK1]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst]
connect_bd_net -net sys_100m_resetn [get_bd_ports eth_phy_rst_n]
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_MDC] [get_bd_ports eth_mdio_mdc]
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_O] [get_bd_ports eth_mdio_o]
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_T] [get_bd_ports eth_mdio_t]
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_I] [get_bd_ports eth_mdio_i]
# phy 1
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth1/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0]
connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc]
connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w]
connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r]
# phy 2
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1]
connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc]
connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w]
connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_r]
# xadc
#connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source
#connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source
#connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0]
#connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8]
#connect_bd_net -net xadc_muxout [get_bd_pins /xadc_core/muxaddr_out] [get_bd_ports muxaddr_out]
# iic
connect_bd_net -net sys_100m_clk [get_bd_pins iic_ee2/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins iic_ee2/s_axi_aresetn]
connect_bd_intf_net [get_bd_intf_pins iic_ee2/IIC] [get_bd_intf_ports iic_ee2]
connect_bd_net -net iic_ee2_irq [get_bd_pins iic_ee2/iic2intc_irpt] [get_bd_ports iic_ee2_intr]
# spi
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_sclk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_sclk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
# cpu interconnect
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M16_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M17_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M18_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M19_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M20_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M16_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M17_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M18_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M19_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M20_ARESETN] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins iic_ee2/S_AXI] -boundary_type upper [get_bd_intf_pins axi_cpu_interconnect/M07_AXI]
# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins speed_detector_m1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins speed_detector_m1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins speed_detector_m2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins speed_detector_m2_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins current_monitor_m1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins current_monitor_m1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins current_monitor_m2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins current_monitor_m2_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m17_axi [get_bd_intf_pins axi_cpu_interconnect/M17_AXI] [get_bd_intf_pins controller_m1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m18_axi [get_bd_intf_pins axi_cpu_interconnect/M18_AXI] [get_bd_intf_pins controller_m1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m19_axi [get_bd_intf_pins axi_cpu_interconnect/M19_AXI] [get_bd_intf_pins controller_m2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m20_axi [get_bd_intf_pins axi_cpu_interconnect/M20_AXI] [get_bd_intf_pins controller_m2_dma/s_axi]
# mem interconnect
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins speed_detector_m1_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins speed_detector_m2_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins current_monitor_m1_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins current_monitor_m2_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s04_axi [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins controller_m1_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s05_axi [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins controller_m2_dma/m_dest_axi]
# address map
create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m1/s_axi/axi_lite] SEG_data_s_d1
create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m1/s_axi/axi_lite] SEG_data_c_m1
create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m1/s_axi/axi_lite] SEG_data_c1
create_bd_addr_seg -range 0x10000 -offset 0x40440000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2/s_axi/axi_lite] SEG_data_s_d2
create_bd_addr_seg -range 0x10000 -offset 0x40450000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2/s_axi/axi_lite] SEG_data_c_m2
create_bd_addr_seg -range 0x10000 -offset 0x40460000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2/s_axi/axi_lite] SEG_data_c2
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m1_dma/s_axi/axi_lite] SEG_data_s_d1_dma
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m1_dma/s_axi/axi_lite] SEG_data_c_m1_dma
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m1_dma/s_axi/axi_lite] SEG_data_c1_dma
create_bd_addr_seg -range 0x10000 -offset 0x40540000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2_dma/s_axi/axi_lite] SEG_data_s_d2_dma
create_bd_addr_seg -range 0x10000 -offset 0x40550000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2_dma/s_axi/axi_lite] SEG_data_c_m2_dma
create_bd_addr_seg -range 0x10000 -offset 0x40560000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2_dma/s_axi/axi_lite] SEG_data_c2_dma
# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc
create_bd_addr_seg -range 0x10000 -offset 0x41510000 $sys_addr_cntrl_space [get_bd_addr_segs iic_ee2/S_AXI/Reg] SEG_iic_ee2_Reg
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces current_monitor_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces current_monitor_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces controller_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces controller_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm

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projects/motcon2_fmc/zed/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/motcon2_fmc_bd.tcl

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projects/motcon2_fmc/zed/system_constr.xdc Normal file
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#DEBUG
# Motor Control
#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}]
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[2]}]
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ; #M2_SENSOR_A
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ; #M2_SENSOR_B
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ; #M2_SENSOR_C
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports vt_enable]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports fmc_m1_en_o]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o]
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o]
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o]
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o]
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o]
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o]
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o]
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 } [get_ports adc_clk_o]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 } [get_ports adc_m1_vbus_dat_i]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 } [get_ports adc_m2_vbus_dat_i]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ia_dat_i]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ib_dat_i]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ia_dat_i]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ib_dat_i]
# GPO
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 } [get_ports {gpo[0]}]
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25 } [get_ports {gpo[1]}]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25 } [get_ports {gpo[2]}]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}]
# GPI
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}]
#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}]
#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}]
#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}]
#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}]
#set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0]
#set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8]
#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0]
#set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8]
# SPI
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ]
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_miso ]
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_mosi ]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sck ]
#FMC_SAMPLE_N
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports fmc_sample_n]
# IIC
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_scl_io]
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_sda_io]
# Ethernet common
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth_mdio_mdc]
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25 PULLUP true} [get_ports eth_mdio_io]
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth_phy_rst_n]
# Ethernet 1
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}]
# Ethernet 2
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}]
# Ethernet common
set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl]
set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1]
set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1]
set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2]
set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2]
set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1]
set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1]
set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3]
set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3]
set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1]
set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1]
# Ethernet 1
# Clock Period Constraints
create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1]
#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1]
create_clock -name eth1_rx_clk_vir -period 8
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -setup
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -setup
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -hold
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -hold
set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -setup 0
set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -hold -1
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}]
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}]
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay
# Ethernet 2
# Clock Period Constraints
create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc]
#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1]
#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1]
create_clock -name eth2_rx_clk_vir -period 8
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3]
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -setup
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -setup
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -hold
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -hold
set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -setup 0
set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -hold -1
set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup
set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup
set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold
set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}]
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}]
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay

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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
eth1_rgmii_rd,
eth1_rgmii_rx_ctl,
eth1_rgmii_rxc,
eth1_rgmii_td,
eth1_rgmii_tx_ctl,
eth1_rgmii_txc,
eth2_rgmii_rd,
eth2_rgmii_rx_ctl,
eth2_rgmii_rxc,
eth2_rgmii_td,
eth2_rgmii_tx_ctl,
eth2_rgmii_txc,
eth_mdio_io,
eth_mdio_mdc,
eth_phy_rst_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
position_m1_i,
position_m2_i,
adc_clk_o,
adc_m1_ia_dat_i,
adc_m1_ib_dat_i,
adc_m1_vbus_dat_i,
fmc_m1_en_o,
fmc_m2_en_o,
adc_m2_ia_dat_i,
adc_m2_ib_dat_i,
adc_m2_vbus_dat_i,
pwm_m1_ah_o,
pwm_m1_al_o,
pwm_m1_bh_o,
pwm_m1_bl_o,
pwm_m1_ch_o,
pwm_m1_cl_o,
pwm_m1_dh_o,
pwm_m1_dl_o,
pwm_m2_ah_o,
pwm_m2_al_o,
pwm_m2_bh_o,
pwm_m2_bl_o,
pwm_m2_ch_o,
pwm_m2_cl_o,
pwm_m2_dh_o,
pwm_m2_dl_o,
vt_enable,
/* vauxn0,
vauxn8,
vauxp0,
vauxp8,
muxaddr_out,*/
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
iic_ee2_scl_io,
iic_ee2_sda_io,
fmc_spi1_sel1_rdc,
fmc_spi1_miso,
fmc_spi1_mosi,
fmc_spi1_sck,
fmc_sample_n,
gpo,
gpi,
otg_vbusoc);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
input [3:0] eth1_rgmii_rd;
input eth1_rgmii_rx_ctl;
input eth1_rgmii_rxc;
output [3:0] eth1_rgmii_td;
output eth1_rgmii_tx_ctl;
output eth1_rgmii_txc;
input [3:0] eth2_rgmii_rd;
input eth2_rgmii_rx_ctl;
input eth2_rgmii_rxc;
output [3:0] eth2_rgmii_td;
output eth2_rgmii_tx_ctl;
output eth2_rgmii_txc;
inout eth_mdio_io;
output eth_mdio_mdc;
output eth_phy_rst_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
input [2:0] position_m1_i;
input [2:0] position_m2_i;
output adc_clk_o;
output fmc_m1_en_o;
input adc_m1_ia_dat_i;
input adc_m1_ib_dat_i;
input adc_m1_vbus_dat_i;
output fmc_m2_en_o;
input adc_m2_ia_dat_i;
input adc_m2_ib_dat_i;
input adc_m2_vbus_dat_i;
output pwm_m1_ah_o;
output pwm_m1_al_o;
output pwm_m1_bh_o;
output pwm_m1_bl_o;
output pwm_m1_ch_o;
output pwm_m1_cl_o;
output pwm_m1_dh_o;
output pwm_m1_dl_o;
output pwm_m2_ah_o;
output pwm_m2_al_o;
output pwm_m2_bh_o;
output pwm_m2_bl_o;
output pwm_m2_ch_o;
output pwm_m2_cl_o;
output pwm_m2_dh_o;
output pwm_m2_dl_o;
output vt_enable;
/* input vauxn0;
input vauxn8;
input vauxp0;
input vauxp8;
output [ 3:0] muxaddr_out;*/
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
inout iic_ee2_scl_io;
inout iic_ee2_sda_io;
output fmc_spi1_sel1_rdc;
input fmc_spi1_miso;
output fmc_spi1_mosi;
output fmc_spi1_sck;
output fmc_sample_n;
output [ 3:0] gpo;
input [ 1:0] gpi;
input otg_vbusoc;
// internal signals
wire [34:0] gpio_i;
wire [34:0] gpio_o;
wire [34:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [15:0] ps_intrs;
wire refclk;
wire refclk_rst;
wire eth_mdio_o;
wire eth_mdio_i;
wire eth_mdio_t;
reg idelayctrl_reset;
reg [ 3:0] idelay_reset_cnt;
// assignments
assign fmc_sample_n = gpio_o[32];
assign gpio_i[34:33] = gpi[1:0];
assign vt_enable = 1'b1;
assign pwm_m1_dh_o = 1'b0;
assign pwm_m1_dl_o = 1'b0;
assign pwm_m2_dh_o = 1'b0;
assign pwm_m2_dl_o = 1'b0;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32))
i_gpio_bd (
.dt(gpio_t[31:0]),
.di(gpio_o[31:0]),
.do(gpio_i[31:0]),
.dio(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_scl (
.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.di(iic_mux_scl_o_s),
.do(iic_mux_scl_i_s),
.dio(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_sda (
.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.di(iic_mux_sda_o_s),
.do(iic_mux_sda_i_s),
.dio(iic_mux_sda));
ad_iobuf #(
.DATA_WIDTH(1))
i_mdio_io (
.dt(eth_mdio_t),
.di(eth_mdio_o),
.do(eth_mdio_i),
.dio(eth_mdio_io));
always @(posedge refclk) begin
if (refclk_rst == 1'b1) begin
idelay_reset_cnt <= 4'h0;
idelayctrl_reset <= 1'b1;
end else begin
idelayctrl_reset <= 1'b1;
case (idelay_reset_cnt)
4'h0: idelay_reset_cnt <= 4'h1;
4'h1: idelay_reset_cnt <= 4'h2;
4'h2: idelay_reset_cnt <= 4'h3;
4'h3: idelay_reset_cnt <= 4'h4;
4'h4: idelay_reset_cnt <= 4'h5;
4'h5: idelay_reset_cnt <= 4'h6;
4'h6: idelay_reset_cnt <= 4'h7;
4'h7: idelay_reset_cnt <= 4'h8;
4'h8: idelay_reset_cnt <= 4'h9;
4'h9: idelay_reset_cnt <= 4'ha;
4'ha: idelay_reset_cnt <= 4'hb;
4'hb: idelay_reset_cnt <= 4'hc;
4'hc: idelay_reset_cnt <= 4'hd;
4'hd: idelay_reset_cnt <= 4'he;
default: begin
idelay_reset_cnt <= 4'he;
idelayctrl_reset <= 1'b0;
end
endcase
end
end
IDELAYCTRL dlyctrl (
.RDY(),
.REFCLK(refclk),
.RST(idelayctrl_reset));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.eth1_rgmii_rd(eth1_rgmii_rd),
.eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl),
.eth1_rgmii_rxc(eth1_rgmii_rxc),
.eth1_rgmii_td(eth1_rgmii_td),
.eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl),
.eth1_rgmii_txc(eth1_rgmii_txc),
.eth2_rgmii_rd(eth2_rgmii_rd),
.eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl),
.eth2_rgmii_rxc(eth2_rgmii_rxc),
.eth2_rgmii_td(eth2_rgmii_td),
.eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl),
.eth2_rgmii_txc(eth2_rgmii_txc),
.eth_phy_rst_n(eth_phy_rst_n),
.eth_mdio_o(eth_mdio_o),
.eth_mdio_t(eth_mdio_t),
.eth_mdio_i(eth_mdio_i),
.eth_mdio_mdc(eth_mdio_mdc),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.position_m1_i(position_m1_i),
.position_m2_i(position_m2_i),
.adc_clk_o(adc_clk_o),
.fmc_m1_en_o(fmc_m1_en_o),
.adc_m1_ia_dat_i(adc_m1_ia_dat_i),
.adc_m1_ib_dat_i(adc_m1_ib_dat_i),
.adc_m1_vbus_dat_i(adc_m1_vbus_dat_i),
.fmc_m2_en_o(fmc_m2_en_o),
.adc_m2_ia_dat_i(adc_m2_ia_dat_i),
.adc_m2_ib_dat_i(adc_m2_ib_dat_i),
.adc_m2_vbus_dat_i(adc_m2_vbus_dat_i),
.gpo_o(gpo),
.pwm_m1_ah_o(pwm_m1_ah_o),
.pwm_m1_al_o(pwm_m1_al_o),
.pwm_m1_bh_o(pwm_m1_bh_o),
.pwm_m1_bl_o(pwm_m1_bl_o),
.pwm_m1_ch_o(pwm_m1_ch_o),
.pwm_m1_cl_o(pwm_m1_cl_o),
.pwm_m2_ah_o(pwm_m2_ah_o),
.pwm_m2_al_o(pwm_m2_al_o),
.pwm_m2_bh_o(pwm_m2_bh_o),
.pwm_m2_bl_o(pwm_m2_bl_o),
.pwm_m2_ch_o(pwm_m2_ch_o),
.pwm_m2_cl_o(pwm_m2_cl_o),
/* .Vaux0_v_n(vauxn0),
.Vaux0_v_p(vauxp0),
.Vaux8_v_n(vauxn8),
.Vaux8_v_p(vauxp8),
.muxaddr_out(muxaddr_out),*/
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.iic_fmc_intr(ps_intrs[13]),
.iic_ee2_intr(ps_intrs[12]),
.motcon2_s_d1_intr(ps_intrs[11]),
.motcon2_c_m1_intr(ps_intrs[10]),
.motcon2_ctrl_m1_intr(ps_intrs[9]),
.motcon2_s_d2_intr(ps_intrs[8]),
.motcon2_c_m2_intr(ps_intrs[7]),
.motcon2_ctrl_m2_intr(ps_intrs[6]),
.iic_ee2_scl_io(iic_ee2_scl_io),
.iic_ee2_sda_io(iic_ee2_sda_io),
.spi_csn_i (1'b1),
.spi_csn_o (fmc_spi1_sel1_rdc),
.spi_miso_i (fmc_spi1_miso),
.spi_mosi_i (1'b0),
.spi_mosi_o (fmc_spi1_mosi),
.spi_sclk_i (1'b0),
.spi_sclk_o (fmc_spi1_sck),
.refclk(refclk),
.refclk_rst(refclk_rst),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************