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jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps

main
Adrian Costina 2017-10-25 14:36:54 +01:00
parent de5a21af80
commit 1b1edd1b03
4 changed files with 34 additions and 3 deletions
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7
library/altera/adi_jesd204/adi_jesd204_hw.tcl
View File

@ -237,6 +237,12 @@ proc jesd204_compose {} {
return
}
if {$lane_rate > 10000} {
set register_inputs 1;
} else {
set register_inputs 0;
}
add_instance sys_clock clock_source
set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000]
set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert}
@ -320,6 +326,7 @@ proc jesd204_compose {} {
set_instance_parameter_value phy LANE_RATE $lane_rate
set_instance_parameter_value phy REFCLK_FREQUENCY $refclk_frequency
set_instance_parameter_value phy NUM_OF_LANES $num_of_lanes
set_instance_parameter_value phy REGISTER_INPUTS $register_inputs
add_connection link_clock.out_clk_1 phy.link_clk
add_connection link_reset.out_reset phy.link_reset

3
library/altera/jesd204_phy/jesd204_phy_hw.tcl
View File

@ -67,6 +67,7 @@ ad_ip_parameter TX_OR_RX_N BOOLEAN false false
ad_ip_parameter LANE_RATE FLOAT 10000 false
ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false
ad_ip_parameter NUM_OF_LANES POSITIVE 4 false
ad_ip_parameter REGISTER_INPUTS INTEGER 0 false
proc jesd204_phy_composition_callback {} {
set soft_pcs [get_parameter_value "SOFT_PCS"]
@ -75,6 +76,7 @@ proc jesd204_phy_composition_callback {} {
set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
set id [get_parameter_value "ID"]
set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set register_inputs [get_parameter_value "REGISTER_INPUTS"]
set link_clk_frequency [expr $lane_rate / 40]
@ -214,6 +216,7 @@ proc jesd204_phy_composition_callback {} {
} else {
if {$soft_pcs} {
add_instance soft_pcs_${i} jesd204_soft_pcs_rx
set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs
add_connection link_clock.clk soft_pcs_${i}.clock
add_connection link_clock.clk_reset soft_pcs_${i}.reset
add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data

25
library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
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@ -44,7 +44,8 @@
module jesd204_soft_pcs_rx #(
parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 4
parameter DATA_PATH_WIDTH = 4,
parameter REGISTER_INPUTS = 0
) (
input clk,
input reset,
@ -71,6 +72,9 @@ wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s;
reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}};
wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
wire patternalign_en_s;
always @(posedge clk) begin
char <= char_s;
charisk <= charisk_s;
@ -81,6 +85,21 @@ end
generate
genvar lane;
genvar i;
if (REGISTER_INPUTS == 1) begin
reg patternalign_en_r;
reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_r;
always @(posedge clk) begin
patternalign_en_r <= patternalign_en;
data_r <= data;
end
assign patternalign_en_s = patternalign_en_r;
assign data_s = data_r;
end else begin
assign patternalign_en_s = patternalign_en;
assign data_s = data;
end
for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
jesd204_pattern_align #(
@ -89,8 +108,8 @@ for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
.clk(clk),
.reset(reset),
.patternalign_en(patternalign_en),
.in_data(data[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]),
.patternalign_en(patternalign_en_s),
.in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]),
.out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])
);

2
library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
View File

@ -49,6 +49,8 @@ source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS"
ad_ip_parameter REGISTER_INPUTS INTEGER 0
set_module_property INTERNAL true
# files