From 1bd444b47f0196a8a183447680e7d07aeaed5bc9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 4 May 2017 13:43:39 -0400 Subject: [PATCH] axi_fmcadc5_sync- calcor added --- library/axi_fmcadc5_sync/axi_fmcadc5_sync.v | 174 +++++++++- .../axi_fmcadc5_sync_calcor.v | 313 ++++++++++++++++++ .../axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl | 2 + 3 files changed, 482 insertions(+), 7 deletions(-) create mode 100644 library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v index 4c054172f..90bb3e289 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v @@ -54,11 +54,12 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( output rx_sync_0_n, output rx_sync_1_p, output rx_sync_1_n, + input [511:0] rx_data, + output [511:0] rx_cor_data, // calibration signal output vcal, - output vcal_enable, // switching regulator clocks @@ -112,10 +113,24 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( reg [ 7:0] up_psync_count = 'd0; reg up_psync = 'd0; + reg up_cal_done_t_m1 = 'd0; + reg up_cal_done_t_m2 = 'd0; + reg up_cal_done_t_m3 = 'd0; + reg [ 15:0] up_cal_max_0 = 'd0; + reg [ 15:0] up_cal_min_0 = 'd0; + reg [ 15:0] up_cal_max_1 = 'd0; + reg [ 15:0] up_cal_min_1 = 'd0; + reg up_cal_enable = 'd0; + reg up_cor_enable = 'd0; + reg up_cor_enable_t = 'd0; + reg [ 15:0] up_cor_scale_0 = 'd0; + reg [ 15:0] up_cor_offset_0 = 'd0; + reg [ 15:0] up_cor_scale_1 = 'd0; + reg [ 15:0] up_cor_offset_1 = 'd0; reg [ 7:0] up_vcal_8 = 'd0; reg up_vcal = 'd0; reg [ 7:0] up_vcal_cnt = 'd0; - reg [ 1:0] up_vcal_enable = 'd0; + reg up_vcal_enable = 'd0; reg up_sysref_ack_t_m1 = 'd0; reg up_sysref_ack_t_m2 = 'd0; reg up_sysref_ack_t_m3 = 'd0; @@ -150,6 +165,20 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( reg up_wack = 'd0; reg up_rack = 'd0; reg [ 31:0] up_rdata = 'd0; + reg rx_cal_enable_m1 = 'd0; + reg rx_cal_enable = 'd0; + reg rx_cor_enable_t_m1 = 'd0; + reg rx_cor_enable_t_m2 = 'd0; + reg rx_cor_enable_t_m3 = 'd0; + reg rx_cor_enable = 'd0; + reg [ 15:0] rx_cor_scale_0 = 'd0; + reg [ 15:0] rx_cor_offset_0 = 'd0; + reg [ 15:0] rx_cor_scale_1 = 'd0; + reg [ 15:0] rx_cor_offset_1 = 'd0; + reg [ 15:0] rx_cor_scale_d_0 = 'd0; + reg [ 15:0] rx_cor_offset_d_0 = 'd0; + reg [ 15:0] rx_cor_scale_d_1 = 'd0; + reg [ 15:0] rx_cor_offset_d_1 = 'd0; reg [ 7:0] rx_sysref_cnt = 'd0; reg rx_sysref_control_t_m1 = 'd0; reg rx_sysref_control_t_m2 = 'd0; @@ -182,11 +211,18 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( // internal signals + wire up_cal_done_t_s; wire up_sysref_ack_t_s; wire up_sync_status_t_s; wire up_spi_gnt_s; wire [ 31:0] up_spi_out_32_s; wire [ 7:0] up_spi_in_s; + wire rx_cor_enable_t_s; + wire rx_cal_done_t_s; + wire [ 15:0] rx_cal_max_0_s; + wire [ 15:0] rx_cal_min_0_s; + wire [ 15:0] rx_cal_max_1_s; + wire [ 15:0] rx_cal_min_1_s; wire rx_sysref_control_t_s; wire rx_sysref_req_t_s; wire rx_sysref_enb_e_s; @@ -226,21 +262,84 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( end end + // calibration (offset & gain only) + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_cal_done_t_m1 <= 1'd0; + up_cal_done_t_m2 <= 1'd0; + up_cal_done_t_m3 <= 1'd0; + end else begin + up_cal_done_t_m1 <= rx_cal_done_t_s; + up_cal_done_t_m2 <= up_cal_done_t_m1; + up_cal_done_t_m3 <= up_cal_done_t_m2; + end + end + + assign up_cal_done_t_s = up_cal_done_t_m3 ^ up_cal_done_t_m2; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_cal_max_0 <= 16'd0; + up_cal_min_0 <= 16'd0; + up_cal_max_1 <= 16'd0; + up_cal_min_1 <= 16'd0; + end else begin + if (up_cal_done_t_s == 1'b1) begin + up_cal_max_0 <= rx_cal_max_0_s; + up_cal_min_0 <= rx_cal_min_0_s; + up_cal_max_1 <= rx_cal_max_1_s; + up_cal_min_1 <= rx_cal_min_1_s; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_cal_enable <= 1'd0; + up_cor_enable <= 1'd0; + up_cor_enable_t <= 1'd0; + up_cor_scale_0 <= 16'd0; + up_cor_offset_0 <= 16'd0; + up_cor_scale_1 <= 16'd0; + up_cor_offset_1 <= 16'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0060)) begin + up_cal_enable <= up_wdata_s[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0061)) begin + up_cor_enable <= up_wdata_s[0]; + up_cor_enable_t <= ~up_cor_enable_t; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0068)) begin + up_cor_scale_0 <= up_wdata_s[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0068)) begin + up_cor_offset_0 <= up_wdata_s[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0068)) begin + up_cor_scale_1 <= up_wdata_s[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0068)) begin + up_cor_offset_1 <= up_wdata_s[15:0]; + end + end + end + // calibration signal register(s) assign vcal = up_vcal; - assign vcal_enable = up_vcal_enable[0]; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin up_vcal_8 <= 8'd0; up_vcal <= 1'd0; up_vcal_cnt <= 8'd0; - up_vcal_enable <= 2'd0; + up_vcal_enable <= 1'd0; end else begin if (up_vcal_8 >= up_vcal_cnt) begin up_vcal_8 <= 8'd0; - up_vcal <= ~up_vcal & up_vcal_enable[1]; + up_vcal <= ~up_vcal & up_vcal_enable; end else begin up_vcal_8 <= up_vcal_8 + 1'b1; up_vcal <= up_vcal; @@ -249,7 +348,7 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( up_vcal_cnt <= up_wdata_s[7:0]; end if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0051)) begin - up_vcal_enable <= up_wdata_s[1:0]; + up_vcal_enable <= up_wdata_s[0]; end end end @@ -480,7 +579,17 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( 14'h0040: up_rdata <= {26'd0, up_sysref_mode_e, 3'b0, up_sysref_mode_i}; 14'h0041: up_rdata <= {31'd0, up_sysref_status}; 14'h0050: up_rdata <= {24'd0, up_vcal_cnt}; - 14'h0051: up_rdata <= {30'd0, up_vcal_enable}; + 14'h0051: up_rdata <= {31'd0, up_vcal_enable}; + 14'h0060: up_rdata <= {30'd0, up_cal_enable}; + 14'h0061: up_rdata <= {30'd0, up_cor_enable}; + 14'h0064: up_rdata <= {16'd0, up_cal_max_0}; + 14'h0065: up_rdata <= {16'd0, up_cal_min_0}; + 14'h0066: up_rdata <= {16'd0, up_cal_max_1}; + 14'h0067: up_rdata <= {16'd0, up_cal_min_1}; + 14'h0068: up_rdata <= {16'd0, up_cor_scale_0}; + 14'h0069: up_rdata <= {16'd0, up_cor_offset_0}; + 14'h006a: up_rdata <= {16'd0, up_cor_scale_1}; + 14'h006b: up_rdata <= {16'd0, up_cor_offset_1}; default: up_rdata <= 0; endcase end else begin @@ -489,6 +598,57 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( end end + // calibration at receive clock + + always @(posedge rx_clk) begin + rx_cal_enable_m1 <= up_cal_enable; + rx_cal_enable <= rx_cal_enable_m1; + rx_cor_enable_t_m1 <= up_cor_enable_t; + rx_cor_enable_t_m2 <= rx_cor_enable_t_m1; + rx_cor_enable_t_m3 <= rx_cor_enable_t_m2; + end + + assign rx_cor_enable_t_s = rx_cor_enable_t_m3 ^ rx_cor_enable_t_m2; + + always @(posedge rx_clk) begin + if (rx_cor_enable_t_s == 1'b1) begin + rx_cor_enable <= up_cor_enable; + rx_cor_scale_0 <= up_cor_scale_0; + rx_cor_offset_0 <= up_cor_offset_0; + rx_cor_scale_1 <= up_cor_scale_1; + rx_cor_offset_1 <= up_cor_offset_1; + end + end + + always @(posedge rx_clk) begin + if (rx_cor_enable == 1'b0) begin + rx_cor_scale_d_0 <= 16'h8000; + rx_cor_offset_d_0 <= 16'h0000; + rx_cor_scale_d_1 <= 16'h8000; + rx_cor_offset_d_1 <= 16'h0000; + end else begin + rx_cor_scale_d_0 <= rx_cor_scale_0; + rx_cor_offset_d_0 <= rx_cor_offset_0; + rx_cor_scale_d_1 <= rx_cor_scale_1; + rx_cor_offset_d_1 <= rx_cor_offset_1; + end + end + + axi_fmcadc5_sync_calcor i_calcor ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .rx_cor_data (rx_cor_data), + .rx_cal_enable (rx_cal_enable), + .rx_cal_done_t (rx_cal_done_t_s), + .rx_cal_max_0 (rx_cal_max_0_s), + .rx_cal_min_0 (rx_cal_min_0_s), + .rx_cal_max_1 (rx_cal_max_1_s), + .rx_cal_min_1 (rx_cal_min_1_s), + .rx_cor_scale_0 (rx_cor_scale_d_0), + .rx_cor_offset_0 (rx_cor_offset_d_0), + .rx_cor_scale_1 (rx_cor_scale_d_1), + .rx_cor_offset_1 (rx_cor_offset_d_1)); + // sysref-control at receive clock always @(posedge rx_clk) begin diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v new file mode 100644 index 000000000..d73698f5c --- /dev/null +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v @@ -0,0 +1,313 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// poor man's version of calibration & correction (scale & offset only) +// assumes linear frequency response on all discrete components +// looking for a rich man's version? fidus.com (FSF-AD15000A) + +`timescale 1ns/100ps + +module axi_fmcadc5_sync_calcor ( + + // receive interface + + input rx_clk, + input [511:0] rx_data, + output [511:0] rx_cor_data, + + // calibration signals + + input rx_cal_enable, + output rx_cal_done_t, + output [ 15:0] rx_cal_max_0, + output [ 15:0] rx_cal_min_0, + output [ 15:0] rx_cal_max_1, + output [ 15:0] rx_cal_min_1, + input [ 15:0] rx_cor_scale_0, + input [ 15:0] rx_cor_offset_0, + input [ 15:0] rx_cor_scale_1, + input [ 15:0] rx_cor_offset_1); + + // internal registers + + reg [ 15:0] rx_cor_data_0[0:15]; + reg [ 15:0] rx_cor_data_1[0:15]; + reg rx_cal_done_int_t = 'd0; + reg [ 15:0] rx_cal_max_0_6 = 'd0; + reg [ 15:0] rx_cal_min_0_6 = 'd0; + reg [ 15:0] rx_cal_max_1_6 = 'd0; + reg [ 15:0] rx_cal_min_1_6 = 'd0; + reg [ 15:0] rx_cal_max_0_5 = 'd0; + reg [ 15:0] rx_cal_min_0_5 = 'd0; + reg [ 15:0] rx_cal_max_1_5 = 'd0; + reg [ 15:0] rx_cal_min_1_5 = 'd0; + reg [ 15:0] rx_cal_max_0_4[0:1]; + reg [ 15:0] rx_cal_min_0_4[0:1]; + reg [ 15:0] rx_cal_max_1_4[0:1]; + reg [ 15:0] rx_cal_min_1_4[0:1]; + reg [ 15:0] rx_cal_max_0_3[0:3]; + reg [ 15:0] rx_cal_min_0_3[0:3]; + reg [ 15:0] rx_cal_max_1_3[0:3]; + reg [ 15:0] rx_cal_min_1_3[0:3]; + reg [ 15:0] rx_cal_max_0_2[0:7]; + reg [ 15:0] rx_cal_min_0_2[0:7]; + reg [ 15:0] rx_cal_max_1_2[0:7]; + reg [ 15:0] rx_cal_min_1_2[0:7]; + reg [ 15:0] rx_cal_max_0_1[0:15]; + reg [ 15:0] rx_cal_min_0_1[0:15]; + reg [ 15:0] rx_cal_max_1_1[0:15]; + reg [ 15:0] rx_cal_min_1_1[0:15]; + + // internal signals + + wire [ 33:0] rx_cor_data_0_s[0:15]; + wire [ 33:0] rx_cor_data_1_s[0:15]; + wire [ 15:0] rx_data_0_s[0:15]; + wire [ 15:0] rx_data_1_s[0:15]; + + // iterations + + genvar n; + + // offset & gain + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data + assign rx_cor_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15]; + assign rx_cor_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15]; + end + endgenerate + + // gain + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_gain + ad_mul #(.DELAY_DATA_WIDTH(1)) i_rx_gain_0 ( + .clk (rx_clk), + .data_a ({rx_cor_data_0[n][15], rx_cor_data_0[n]}), + .data_b ({1'b0, rx_cor_scale_0}), + .data_p (rx_cor_data_0_s[n]), + .ddata_in (1'd0), + .ddata_out ()); + ad_mul #(.DELAY_DATA_WIDTH(1)) i_rx_gain_1 ( + .clk (rx_clk), + .data_a ({rx_cor_data_1[n][15], rx_cor_data_1[n]}), + .data_b ({1'b0, rx_cor_scale_1}), + .data_p (rx_cor_data_1_s[n]), + .ddata_in (1'd0), + .ddata_out ()); + end + endgenerate + + // offset + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_offset + always @(posedge rx_clk) begin + rx_cor_data_0[n] <= rx_data_0_s[n] + rx_cor_offset_0; + rx_cor_data_1[n] <= rx_data_1_s[n] + rx_cor_offset_1; + end + end + endgenerate + + // calibration peaks + + assign rx_cal_done_t = rx_cal_done_int_t; + assign rx_cal_max_0 = rx_cal_max_0_6; + assign rx_cal_min_0 = rx_cal_min_0_6; + assign rx_cal_max_1 = rx_cal_max_1_6; + assign rx_cal_min_1 = rx_cal_min_1_6; + + always @(posedge rx_clk) begin + if (rx_cal_enable == 1'b1) begin + rx_cal_done_int_t <= ~rx_cal_done_int_t; + rx_cal_max_0_6 <= rx_cal_max_0_5; + rx_cal_min_0_6 <= rx_cal_min_0_5; + rx_cal_max_1_6 <= rx_cal_max_1_5; + rx_cal_min_1_6 <= rx_cal_min_1_5; + end + end + + // run-time peaks + + always @(posedge rx_clk) begin + if (rx_cal_max_0_4[1] > rx_cal_max_0_4[0]) begin + rx_cal_max_0_5 <= rx_cal_max_0_4[1]; + end else begin + rx_cal_max_0_5 <= rx_cal_max_0_4[0]; + end + if (rx_cal_min_0_4[1] < rx_cal_min_0_4[0]) begin + rx_cal_min_0_5 <= rx_cal_min_0_4[1]; + end else begin + rx_cal_min_0_5 <= rx_cal_min_0_4[0]; + end + if (rx_cal_max_1_4[1] > rx_cal_max_1_4[0]) begin + rx_cal_max_1_5 <= rx_cal_max_1_4[1]; + end else begin + rx_cal_max_1_5 <= rx_cal_max_1_4[0]; + end + if (rx_cal_min_1_4[1] < rx_cal_min_1_4[0]) begin + rx_cal_min_1_5 <= rx_cal_min_1_4[1]; + end else begin + rx_cal_min_1_5 <= rx_cal_min_1_4[0]; + end + end + + // peak iterations + + generate + for (n = 0; n <= 1; n = n + 1) begin: g_rx_peak_4 + always @(posedge rx_clk) begin + if (rx_cal_max_0_3[((n*2)+1)] > rx_cal_max_0_3[(n*2)]) begin + rx_cal_max_0_4[n] <= rx_cal_max_0_3[((n*2)+1)]; + end else begin + rx_cal_max_0_4[n] <= rx_cal_max_0_3[(n*2)]; + end + if (rx_cal_min_0_3[((n*2)+1)] < rx_cal_min_0_3[(n*2)]) begin + rx_cal_min_0_4[n] <= rx_cal_min_0_3[((n*2)+1)]; + end else begin + rx_cal_min_0_4[n] <= rx_cal_min_0_3[(n*2)]; + end + if (rx_cal_max_1_3[((n*2)+1)] > rx_cal_max_1_3[(n*2)]) begin + rx_cal_max_1_4[n] <= rx_cal_max_1_3[((n*2)+1)]; + end else begin + rx_cal_max_1_4[n] <= rx_cal_max_1_3[(n*2)]; + end + if (rx_cal_min_1_3[((n*2)+1)] < rx_cal_min_1_3[(n*2)]) begin + rx_cal_min_1_4[n] <= rx_cal_min_1_3[((n*2)+1)]; + end else begin + rx_cal_min_1_4[n] <= rx_cal_min_1_3[(n*2)]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 3; n = n + 1) begin: g_rx_peak_3 + always @(posedge rx_clk) begin + if (rx_cal_max_0_2[((n*2)+1)] > rx_cal_max_0_2[(n*2)]) begin + rx_cal_max_0_3[n] <= rx_cal_max_0_2[((n*2)+1)]; + end else begin + rx_cal_max_0_3[n] <= rx_cal_max_0_2[(n*2)]; + end + if (rx_cal_min_0_2[((n*2)+1)] < rx_cal_min_0_2[(n*2)]) begin + rx_cal_min_0_3[n] <= rx_cal_min_0_2[((n*2)+1)]; + end else begin + rx_cal_min_0_3[n] <= rx_cal_min_0_2[(n*2)]; + end + if (rx_cal_max_1_2[((n*2)+1)] > rx_cal_max_1_2[(n*2)]) begin + rx_cal_max_1_3[n] <= rx_cal_max_1_2[((n*2)+1)]; + end else begin + rx_cal_max_1_3[n] <= rx_cal_max_1_2[(n*2)]; + end + if (rx_cal_min_1_2[((n*2)+1)] < rx_cal_min_1_2[(n*2)]) begin + rx_cal_min_1_3[n] <= rx_cal_min_1_2[((n*2)+1)]; + end else begin + rx_cal_min_1_3[n] <= rx_cal_min_1_2[(n*2)]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 7; n = n + 1) begin: g_rx_peak_2 + always @(posedge rx_clk) begin + if (rx_cal_max_0_1[((n*2)+1)] > rx_cal_max_0_1[(n*2)]) begin + rx_cal_max_0_2[n] <= rx_cal_max_0_1[((n*2)+1)]; + end else begin + rx_cal_max_0_2[n] <= rx_cal_max_0_1[(n*2)]; + end + if (rx_cal_min_0_1[((n*2)+1)] < rx_cal_min_0_1[(n*2)]) begin + rx_cal_min_0_2[n] <= rx_cal_min_0_1[((n*2)+1)]; + end else begin + rx_cal_min_0_2[n] <= rx_cal_min_0_1[(n*2)]; + end + if (rx_cal_max_1_1[((n*2)+1)] > rx_cal_max_1_1[(n*2)]) begin + rx_cal_max_1_2[n] <= rx_cal_max_1_1[((n*2)+1)]; + end else begin + rx_cal_max_1_2[n] <= rx_cal_max_1_1[(n*2)]; + end + if (rx_cal_min_1_1[((n*2)+1)] < rx_cal_min_1_1[(n*2)]) begin + rx_cal_min_1_2[n] <= rx_cal_min_1_1[((n*2)+1)]; + end else begin + rx_cal_min_1_2[n] <= rx_cal_min_1_1[(n*2)]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_peak_1 + always @(posedge rx_clk) begin + if (rx_cal_enable == 1'b0) begin + rx_cal_max_0_1[n] <= 16'h0000; + end else if ((rx_data_0_s[n] > rx_cal_max_0_1[n]) && + (rx_data_0_s[n][15] == 1'b0)) begin + rx_cal_max_0_1[n] <= rx_data_0_s[n]; + end + if (rx_cal_enable == 1'b0) begin + rx_cal_min_0_1[n] <= 16'hffff; + end else if ((rx_data_0_s[n] < rx_cal_min_0_1[n]) && + (rx_data_0_s[n][15] == 1'b1)) begin + rx_cal_min_0_1[n] <= rx_data_0_s[n]; + end + if (rx_cal_enable == 1'b0) begin + rx_cal_max_1_1[n] <= 16'h0000; + end else if ((rx_data_1_s[n] > rx_cal_max_1_1[n]) && + (rx_data_1_s[n][15] == 1'b0)) begin + rx_cal_max_1_1[n] <= rx_data_1_s[n]; + end + if (rx_cal_enable == 1'b0) begin + rx_cal_min_1_1[n] <= 16'hffff; + end else if ((rx_data_1_s[n] < rx_cal_min_1_1[n]) && + (rx_data_1_s[n][15] == 1'b1)) begin + rx_cal_min_1_1[n] <= rx_data_1_s[n]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_data + assign rx_data_0_s[n] = rx_data[((n*32)+15):((n*32)+ 0)]; + assign rx_data_1_s[n] = rx_data[((n*32)+31):((n*32)+16)]; + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl index 70ab72d3f..ebb34fc4b 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl @@ -6,8 +6,10 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_fmcadc5_sync adi_ip_files axi_fmcadc5_sync [list \ "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "axi_fmcadc5_sync_constr.xdc" \ + "axi_fmcadc5_sync_calcor.v" \ "axi_fmcadc5_sync.v" ] adi_ip_properties axi_fmcadc5_sync