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ad9656:Add reference design for the ad9656 eval board (#494) 

Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
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hotoleanudan 2020-10-06 09:53:40 +03:00 committed by GitHub
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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# RX parameters
set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 4 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad9656_rx_xcvr [list \
NUM_OF_LANES $RX_NUM_OF_LANES \
QPLL_ENABLE 1 \
TX_OR_RX_N 0 \
SYS_CLK_SEL 0 \
OUT_CLK_SEL 4 \
]
adi_axi_jesd204_rx_create axi_ad9656_rx_jesd $RX_NUM_OF_LANES
ad_ip_instance util_cpack2 util_ad9656_rx_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_rx_create rx_ad9656_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
ad_ip_instance axi_dmac axi_ad9656_rx_dma [list \
DMA_TYPE_SRC 2 \
DMA_TYPE_DEST 0 \
CYCLIC 0 \
SYNC_TRANSFER_START 1 \
DMA_2D_TRANSFER 0 \
DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES] \
MAX_BYTES_PER_BURST 256 \
AXI_SLICE_DEST false \
AXI_SLICE_SRC false \
DMA_DATA_WIDTH_DEST 128 \
FIFO_SIZE 32 \
]
# common cores
ad_ip_instance util_adxcvr util_ad9656_xcvr [list \
RX_NUM_OF_LANES $RX_NUM_OF_LANES \
TX_NUM_OF_LANES 0 \
CPLL_FBDIV 4 \
CPLL_FBDIV_4_5 5 \
RX_OUT_DIV 2 \
RX_CLK25_DIV 5 \
]
# xcvr interfaces
set rx_ref_clk rx_ref_clk_0
create_bd_port -dir I $rx_ref_clk
ad_connect $sys_cpu_resetn util_ad9656_xcvr/up_rstn
ad_connect $sys_cpu_clk util_ad9656_xcvr/up_clk
# Rx
ad_connect ad9656_rx_device_clk util_ad9656_xcvr/rx_out_clk_0
ad_xcvrcon util_ad9656_xcvr axi_ad9656_rx_xcvr axi_ad9656_rx_jesd {} ad9656_rx_device_clk
ad_xcvrpll $rx_ref_clk util_ad9656_xcvr/qpll_ref_clk_0
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_ad9656_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_ad9656_rx_xcvr/up_pll_rst util_ad9656_xcvr/up_cpll_rst_$ch
}
# connections (adc)
ad_connect util_ad9656_xcvr/rx_out_clk_0 rx_ad9656_tpl_core/link_clk
ad_connect axi_ad9656_rx_jesd/rx_sof rx_ad9656_tpl_core/link_sof
ad_connect axi_ad9656_rx_jesd/rx_data_tdata rx_ad9656_tpl_core/link_data
ad_connect axi_ad9656_rx_jesd/rx_data_tvalid rx_ad9656_tpl_core/link_valid
ad_connect util_ad9656_xcvr/rx_out_clk_0 util_ad9656_rx_cpack/clk
ad_connect ad9656_rx_device_clk_rstgen/peripheral_reset util_ad9656_rx_cpack/reset
ad_connect rx_ad9656_tpl_core/adc_valid_0 util_ad9656_rx_cpack/fifo_wr_en
ad_connect rx_ad9656_tpl_core/adc_enable_0 util_ad9656_rx_cpack/enable_0
ad_connect rx_ad9656_tpl_core/adc_enable_1 util_ad9656_rx_cpack/enable_1
ad_connect rx_ad9656_tpl_core/adc_enable_2 util_ad9656_rx_cpack/enable_2
ad_connect rx_ad9656_tpl_core/adc_enable_3 util_ad9656_rx_cpack/enable_3
ad_connect rx_ad9656_tpl_core/adc_data_0 util_ad9656_rx_cpack/fifo_wr_data_0
ad_connect rx_ad9656_tpl_core/adc_data_1 util_ad9656_rx_cpack/fifo_wr_data_1
ad_connect rx_ad9656_tpl_core/adc_data_2 util_ad9656_rx_cpack/fifo_wr_data_2
ad_connect rx_ad9656_tpl_core/adc_data_3 util_ad9656_rx_cpack/fifo_wr_data_3
ad_connect rx_ad9656_tpl_core/adc_dovf util_ad9656_rx_cpack/fifo_wr_overflow
ad_connect util_ad9656_xcvr/rx_out_clk_0 axi_ad9656_rx_dma/fifo_wr_clk
ad_connect util_ad9656_rx_cpack/packed_fifo_wr axi_ad9656_rx_dma/fifo_wr
ad_connect $sys_dma_resetn axi_ad9656_rx_dma/m_dest_axi_aresetn
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 rx_ad9656_tpl_core
ad_cpu_interconnect 0x44A60000 axi_ad9656_rx_xcvr
ad_cpu_interconnect 0x44AA0000 axi_ad9656_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9656_rx_dma
ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9656_rx_xcvr/m_axi
# interconnect (mem/dac)
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-12 mb-13 axi_ad9656_rx_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9656_rx_dma/irq

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad9656_fmc_zcu102
M_DEPS += ../common/ad9656_fmc_bd.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += sysid_rom
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
ad_mem_hp0_interconnect sys_cpu_clk sys_ps8/S_AXI_HP0
source ../common/ad9656_fmc_bd.tcl

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# ad9656
set_property -dict {PACKAGE_PIN G8} [get_ports ref_clk0_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P
set_property -dict {PACKAGE_PIN G7} [get_ports ref_clk0_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N
set_property -dict {PACKAGE_PIN L8} [get_ports ref_clk1_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P
set_property -dict {PACKAGE_PIN L7} [get_ports ref_clk1_n] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_N
set_property -dict {PACKAGE_PIN J4} [get_ports rx_data_p[0]] ; ## A02 FMC_HPC0_DP1_M2C_P
set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[0]] ; ## A03 FMC_HPC0_DP1_M2C_N
set_property -dict {PACKAGE_PIN F2} [get_ports rx_data_p[1]] ; ## A06 FMC_HPC0_DP2_M2C_P
set_property -dict {PACKAGE_PIN F1} [get_ports rx_data_n[1]] ; ## A07 FMC_HPC0_DP2_M2C_N
set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[2]] ; ## C06 FMC_HPC0_DP0_M2C_P
set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[2]] ; ## C07 FMC_HPC0_DP0_M2C_N
set_property -dict {PACKAGE_PIN K2} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC0_DP3_M2C_P
set_property -dict {PACKAGE_PIN K1} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC0_DP3_M2C_N
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9508] ; ## G09 FMC_HPC0_LA03_P
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9553] ; ## G10 FMC_HPC0_LA03_N
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D08 FMC_HPC0_LA01_CC_P
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## D09 FMC_HPC0_LA01_CC_N
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS} [get_ports sysref_out_p] ; ## D11 FMC_HPC0_LA05_P
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS} [get_ports sysref_out_n] ; ## D12 FMC_HPC0_LA05_N
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H10 FMC_HPC0_LA04_P
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H11 FMC_HPC0_LA04_N
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS} [get_ports sysref_p] ; ## H4 FMC_HPC0_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS} [get_ports sysref_n] ; ## H5 FMC_HPC0_CLK0_M2C_N
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## H7 FMC_HPC0_LA02_P
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9656] ; ## H8 FMC_HPC0_LA02_N
# clocks
create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk0_p]
create_generated_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_ad9656_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
# SYSREF input
set_input_delay -clock [get_clocks rx_div_clk] [get_property PERIOD [get_clocks rx_div_clk]] [get_ports {sysref_n sysref_p}]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9656_fmc_zcu102
adi_project_files ad9656_fmc_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run ad9656_fmc_zcu102

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
input ref_clk0_p,
input ref_clk0_n,
input ref_clk1_p,
input ref_clk1_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output rx_sync_p,
output rx_sync_n,
input sysref_p,
input sysref_n,
output sysref_out_p,
output sysref_out_n,
output spi_csn_ad9508,
output spi_csn_ad9553,
output spi_csn_ad9656,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire [20:0] gpio_bd;
wire [ 2:0] spi_csn;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire sysref;
wire sysref_out;
assign gpio_bd_o = gpio_o[7:0];
assign gpio_i[94:21] = gpio_o[94:21];
assign gpio_i[20: 8] = gpio_bd_i;
assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
assign sysref_out = 0;
// instantiations
IBUFDS_GTE4 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE4 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_sysref_out (
.I (sysref_out),
.O (sysref_out_p),
.OB (sysref_out_n));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
assign spi_csn_ad9656 = spi_csn[0];
assign spi_csn_ad9508 = spi_csn[1];
assign spi_csn_ad9553 = spi_csn[2];
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk0),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (sysref),
.spi0_sclk (spi_clk),
.spi0_csn (spi_csn),
.spi0_miso (spi_miso),
.spi0_mosi (spi_mosi),
.spi1_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi ());
endmodule
// ***************************************************************************
// ***************************************************************************