zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_adc_trigger: Cosmetic update 

Use localparam DW = 15 - SIGN_BITS
main
AndreiGrozav 2019-02-05 07:24:49 +00:00 committed by AndreiGrozav
parent 44e20d095c
commit 1c8172de7f
1 changed files with 94 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
library/axi_adc_trigger/axi_adc_trigger.v
View File

@ -85,6 +85,9 @@ module axi_adc_trigger #(
output [ 1:0] s_axi_rresp,
input s_axi_rready);
localparam DW = 15 - SIGN_BITS;
// internal signals
wire up_clk;
@ -119,10 +122,10 @@ module axi_adc_trigger #(
wire [ 2:0] trigger_out_mix;
wire [31:0] trigger_delay;
wire signed [15-SIGN_BITS:0] data_a_cmp;
wire [15:0] data_b_cmp;
wire signed [15-SIGN_BITS:0] limit_a_cmp;
wire [15:0] limit_b_cmp;
wire signed [DW:0] data_a_cmp;
wire signed [DW:0] data_b_cmp;
wire signed [DW:0] limit_a_cmp;
wire signed [DW:0] limit_b_cmp;
wire comp_low_a_s; // signal is over the limit
wire comp_low_b_s; // signal is over the limit
@ -149,14 +152,14 @@ module axi_adc_trigger #(
reg old_comp_high_a; // t + 1 version of comp_high_a
reg first_a_h_trigger; // valid hysteresis range on passthrough high trigger limit
reg first_a_l_trigger; // valid hysteresis range on passthrough low trigger limit
reg signed [15-SIGN_BITS:0] hyst_a_high_limit;
reg signed [15-SIGN_BITS:0] hyst_a_low_limit;
reg signed [DW:0] hyst_a_high_limit;
reg signed [DW:0] hyst_a_low_limit;
reg comp_high_b; // signal is over the limit
reg old_comp_high_b; // t + 1 version of comp_high_b
reg first_b_h_trigger; // valid hysteresis range on passthrough high trigger limit
reg first_b_l_trigger; // valid hysteresis range on passthrough low trigger limit
reg signed [15-SIGN_BITS:0] hyst_b_high_limit;
reg signed [15-SIGN_BITS:0] hyst_b_low_limit;
reg signed [DW:0] hyst_b_high_limit;
reg signed [DW:0] hyst_b_low_limit;
reg trigger_pin_a;
reg trigger_pin_b;
@ -201,10 +204,10 @@ module axi_adc_trigger #(
assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0;
assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge;
assign data_a_cmp = data_a[15-SIGN_BITS:0];
assign data_b_cmp = data_b[15-SIGN_BITS:0];
assign limit_a_cmp = limit_a[15-SIGN_BITS:0];
assign limit_b_cmp = limit_b[15-SIGN_BITS:0];
assign data_a_cmp = data_a[DW:0];
assign data_b_cmp = data_b[DW:0];
assign limit_a_cmp = limit_a[DW:0];
assign limit_b_cmp = limit_b[DW:0];
assign data_a_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_a_r} : {trigger_out_delayed |streaming_on, data_a_r};
assign data_b_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_b_r} : {trigger_out_delayed |streaming_on, data_b_r};
@ -359,8 +362,8 @@ module axi_adc_trigger #(
always @(posedge clk) begin
if (data_valid_a == 1'b1) begin
hyst_a_high_limit <= limit_a_cmp + hysteresis_a[15-SIGN_BITS:0];
hyst_a_low_limit <= limit_a_cmp - hysteresis_a[15-SIGN_BITS:0];
hyst_a_high_limit <= limit_a_cmp + hysteresis_a[DW:0];
hyst_a_low_limit <= limit_a_cmp - hysteresis_a[DW:0];
if (data_a_cmp >= limit_a_cmp) begin
comp_high_a <= 1'b1;
@ -385,8 +388,8 @@ module axi_adc_trigger #(
always @(posedge clk) begin
if (data_valid_b == 1'b1) begin
hyst_b_high_limit <= limit_b_cmp + hysteresis_b[15-SIGN_BITS:0];
hyst_b_low_limit <= limit_b_cmp - hysteresis_b[15-SIGN_BITS:0];
hyst_b_high_limit <= limit_b_cmp + hysteresis_b[DW:0];
hyst_b_low_limit <= limit_b_cmp - hysteresis_b[DW:0];
if (data_b_cmp >= limit_b_cmp) begin
comp_high_b <= 1'b1;