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fmcadc4: Remove project

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Adrian Costina 2019-05-16 15:10:04 +01:00
parent ec636b785a
commit 1c8e71ec4e
8 changed files with 0 additions and 626 deletions
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6
projects/fmcadc4/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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projects/fmcadc4/common/fmcadc4_bd.tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name axi_ad9680_fifo
set adc_data_width 256
set adc_dma_data_width 64
# fmcadc4
# adc peripherals
ad_ip_instance axi_ad9680 axi_ad9680_core_0
ad_ip_parameter axi_ad9680_core_0 CONFIG.ID 0
ad_ip_instance axi_ad9680 axi_ad9680_core_1
ad_ip_parameter axi_ad9680_core_1 CONFIG.ID 1
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 8
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
adi_axi_jesd204_rx_create axi_ad9680_jesd 8
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
ad_ip_instance util_cpack2 axi_ad9680_cpack { \
NUM_OF_CHANNELS 4 \
SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
# adc common gt
ad_ip_instance util_adxcvr util_fmcadc4_xcvr
ad_ip_parameter util_fmcadc4_xcvr CONFIG.RX_NUM_OF_LANES 8
ad_ip_parameter util_fmcadc4_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_instance util_bsplit util_bsplit_rx_data
ad_ip_parameter util_bsplit_rx_data CONFIG.CHANNEL_DATA_WIDTH 128
ad_ip_parameter util_bsplit_rx_data CONFIG.NUM_OF_CHANNELS 2
# reference clocks & resets
create_bd_port -dir I rx_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_fmcadc4_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_fmcadc4_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_cpll_rst_*
# connections (gt)
ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_jesd/rx_data_tdata util_bsplit_rx_data/data
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
# connections (adc)
ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
for {set i 0} {$i < 2} {incr i} {
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_${i}/rx_clk
ad_connect util_bsplit_rx_data/split_data_${i} axi_ad9680_core_${i}/rx_data
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_${i}/rx_sof
for {set j 0} {$j < 2} {incr j} {
set k [expr $i * 2 + $j]
ad_connect axi_ad9680_core_${i}/adc_enable_${j} axi_ad9680_cpack/enable_${k}
ad_connect axi_ad9680_core_${i}/adc_data_${j} axi_ad9680_cpack/fifo_wr_data_${k}
}
}
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf
ad_connect sys_cpu_clk util_fmcadc4_xcvr/up_clk
ad_connect sys_cpu_resetn util_fmcadc4_xcvr/up_rstn
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9680_xcvr
ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0
ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
# interconnect (mem/adc)
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-12 mb-13 axi_ad9680_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq

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projects/fmcadc4/common/fmcadc4_spi.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcadc4_spi (
input [ 2:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
inout spi_sdio);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/fmcadc4/zc706/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := fmcadc4_zc706
M_DEPS += ../common/fmcadc4_spi.v
M_DEPS += ../common/fmcadc4_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_ad9680
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += util_bsplit
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adcfifo
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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projects/fmcadc4/zc706/system_bd.tcl
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set adc_fifo_address_width 18
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source ../common/fmcadc4_bd.tcl

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projects/fmcadc4/zc706/system_constr.xdc
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# fmcadc4
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[0]] ; ## A14 FMC_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[0]] ; ## A15 FMC_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[1]] ; ## A18 FMC_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[1]] ; ## A19 FMC_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[2]] ; ## B16 FMC_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[2]] ; ## B17 FMC_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[3]] ; ## B12 FMC_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[3]] ; ## B13 FMC_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[4]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[4]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[5]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[5]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[6]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[6]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[7]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[7]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports rx_sync_0_p] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports rx_sync_0_n] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9528_csn] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ada4961_1a_csn] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports ada4961_1b_csn] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports ad9680_1_csn] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports ada4961_2a_csn] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports ada4961_2b_csn] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports ad9680_2_csn] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9528_rstn] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports ad9528_status] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports ad9680_1_fda] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports ad9680_1_fdb] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9680_2_fda] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9680_2_fdb] ; ## H17 FMC_HPC_LA11_N
# clocks
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcadc4_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]

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projects/fmcadc4/zc706/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx fmcadc4_zc706
adi_project_files fmcadc4_zc706 [list \
"../common/fmcadc4_spi.v" \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run fmcadc4_zc706

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projects/fmcadc4/zc706/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
input sys_rst,
input sys_clk_p,
input sys_clk_n,
output [13:0] ddr3_addr,
output [ 2:0] ddr3_ba,
output ddr3_cas_n,
output [ 0:0] ddr3_ck_n,
output [ 0:0] ddr3_ck_p,
output [ 0:0] ddr3_cke,
output [ 0:0] ddr3_cs_n,
output [ 7:0] ddr3_dm,
inout [63:0] ddr3_dq,
inout [ 7:0] ddr3_dqs_n,
inout [ 7:0] ddr3_dqs_p,
output [ 0:0] ddr3_odt,
output ddr3_ras_n,
output ddr3_reset_n,
output ddr3_we_n,
inout iic_scl,
inout iic_sda,
input rx_ref_clk_p,
input rx_ref_clk_n,
input rx_sysref_p,
input rx_sysref_n,
output rx_sync_0_p,
output rx_sync_0_n,
output rx_sync_1_p,
output rx_sync_1_n,
input [ 7:0] rx_data_p,
input [ 7:0] rx_data_n,
inout ad9528_rstn,
inout ad9528_status,
inout ad9680_1_fda,
inout ad9680_1_fdb,
inout ad9680_2_fda,
inout ad9680_2_fdb,
output ad9528_csn,
output ada4961_1a_csn,
output ada4961_1b_csn,
output ad9680_1_csn,
output ada4961_2a_csn,
output ada4961_2b_csn,
output ad9680_2_csn,
output spi_clk,
inout spi_sdio);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
// spi
assign spi_clk = spi0_clk;
assign ad9528_csn = (spi0_csn == 3'b000) ? 1'b0 : 1'b1;
assign ad9680_1_csn = (spi0_csn == 3'b001) ? 1'b0 : 1'b1;
assign ad9680_2_csn = (spi0_csn == 3'b010) ? 1'b0 : 1'b1;
assign ada4961_1a_csn = (spi0_csn == 3'b011) ? 1'b0 : 1'b1;
assign ada4961_1b_csn = (spi0_csn == 3'b100) ? 1'b0 : 1'b1;
assign ada4961_2a_csn = (spi0_csn == 3'b101) ? 1'b0 : 1'b1;
assign ada4961_2b_csn = (spi0_csn == 3'b110) ? 1'b0 : 1'b1;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_rx_sysref (
.I (rx_sysref_p),
.IB (rx_sysref_n),
.O (rx_sysref));
OBUFDS i_obufds_rx_sync_0 (
.I (rx_sync),
.O (rx_sync_0_p),
.OB (rx_sync_0_n));
OBUFDS i_obufds_rx_sync_1 (
.I (rx_sync),
.O (rx_sync_1_p),
.OB (rx_sync_1_n));
fmcadc4_spi i_spi (
.spi_csn (spi0_csn),
.spi_clk (spi_clk),
.spi_mosi (spi0_mosi),
.spi_miso (spi0_miso),
.spi_sdio (spi_sdio));
ad_iobuf #(.DATA_WIDTH(6)) i_iobuf (
.dio_t (gpio_t[37:32]),
.dio_i (gpio_o[37:32]),
.dio_o (gpio_i[37:32]),
.dio_p ({ ad9680_2_fdb, // 37
ad9680_2_fda, // 36
ad9680_1_fdb, // 35
ad9680_1_fda, // 34
ad9528_status, // 33
ad9528_rstn})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
assign gpio_i[63:38] = gpio_o[63:38];
assign gpio_i[31:15] = gpio_o[31:15];
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_data_4_n (rx_data_n[4]),
.rx_data_4_p (rx_data_p[4]),
.rx_data_5_n (rx_data_n[5]),
.rx_data_5_p (rx_data_p[5]),
.rx_data_6_n (rx_data_n[6]),
.rx_data_6_p (rx_data_p[6]),
.rx_data_7_n (rx_data_n[7]),
.rx_data_7_p (rx_data_p[7]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst));
endmodule
// ***************************************************************************
// ***************************************************************************