From 1d223c19f821cdf3e7f3c3cffc184254d5251d4f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 12 Feb 2018 19:04:42 +0100 Subject: [PATCH] fmcadc4: Use new pack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen --- projects/fmcadc4/common/fmcadc4_bd.tcl | 47 ++++++++++++-------------- projects/fmcadc4/zc706/Makefile | 2 +- 2 files changed, 23 insertions(+), 26 deletions(-) diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index f6e58d16b..8300730c3 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -30,9 +30,11 @@ ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64 -ad_ip_instance util_cpack axi_ad9680_cpack -ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64 -ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 4 +ad_ip_instance util_cpack2 axi_ad9680_cpack { \ + NUM_OF_CHANNELS 4 \ + SAMPLES_PER_CHANNEL 4 \ + SAMPLE_DATA_WIDTH 16 \ +} # adc common gt @@ -56,34 +58,29 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_cpll_rst_* # connections (gt) ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd -ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk -ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk -ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk -ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_0/rx_sof -ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_1/rx_sof +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk ad_connect axi_ad9680_jesd/rx_data_tdata util_bsplit_rx_data/data -ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset # connections (adc) -ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data -ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data -ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0 -ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0 -ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0 -ad_connect axi_ad9680_core_0/adc_enable_1 axi_ad9680_cpack/adc_enable_1 -ad_connect axi_ad9680_core_0/adc_valid_1 axi_ad9680_cpack/adc_valid_1 -ad_connect axi_ad9680_core_0/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect axi_ad9680_core_1/adc_enable_0 axi_ad9680_cpack/adc_enable_2 -ad_connect axi_ad9680_core_1/adc_valid_0 axi_ad9680_cpack/adc_valid_2 -ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2 -ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3 -ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3 -ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3 +ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/fifo_wr_en + +for {set i 0} {$i < 2} {incr i} { + ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_${i}/rx_clk + ad_connect util_bsplit_rx_data/split_data_${i} axi_ad9680_core_${i}/rx_data + ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_${i}/rx_sof + for {set j 0} {$j < 2} {incr j} { + set k [expr $i * 2 + $j] + ad_connect axi_ad9680_core_${i}/adc_enable_${j} axi_ad9680_cpack/enable_${k} + ad_connect axi_ad9680_core_${i}/adc_data_${j} axi_ad9680_cpack/fifo_wr_data_${k} + } +} + ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst -ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr -ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata +ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr +ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile index 9e704d0f4..f6fe5aea8 100644 --- a/projects/fmcadc4/zc706/Makefile +++ b/projects/fmcadc4/zc706/Makefile @@ -22,7 +22,7 @@ LIB_DEPS += axi_spdif_tx LIB_DEPS += jesd204/axi_jesd204_rx LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += util_bsplit -LIB_DEPS += util_cpack +LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += xilinx/axi_adcfifo LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr