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fmcadc4: Use new pack infrastructure 

Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-02-12 19:04:42 +01:00 committed by Adrian Costina
parent 1375dcfeaa
commit 1d223c19f8
2 changed files with 23 additions and 26 deletions
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47
projects/fmcadc4/common/fmcadc4_bd.tcl
View File

@ -30,9 +30,11 @@ ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_cpack axi_ad9680_cpack ad_ip_instance util_cpack2 axi_ad9680_cpack { \
ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64 NUM_OF_CHANNELS 4 \
ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 4 SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
# adc common gt # adc common gt
@ -56,34 +58,29 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_cpll_rst_*
# connections (gt) # connections (gt)
ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_0/rx_sof
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_1/rx_sof
ad_connect axi_ad9680_jesd/rx_data_tdata util_bsplit_rx_data/data ad_connect axi_ad9680_jesd/rx_data_tdata util_bsplit_rx_data/data
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
# connections (adc) # connections (adc)
ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data
ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0 for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_${i}/rx_clk
ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect util_bsplit_rx_data/split_data_${i} axi_ad9680_core_${i}/rx_data
ad_connect axi_ad9680_core_0/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_${i}/rx_sof
ad_connect axi_ad9680_core_0/adc_valid_1 axi_ad9680_cpack/adc_valid_1 for {set j 0} {$j < 2} {incr j} {
ad_connect axi_ad9680_core_0/adc_data_1 axi_ad9680_cpack/adc_data_1 set k [expr $i * 2 + $j]
ad_connect axi_ad9680_core_1/adc_enable_0 axi_ad9680_cpack/adc_enable_2 ad_connect axi_ad9680_core_${i}/adc_enable_${j} axi_ad9680_cpack/enable_${k}
ad_connect axi_ad9680_core_1/adc_valid_0 axi_ad9680_cpack/adc_valid_2 ad_connect axi_ad9680_core_${i}/adc_data_${j} axi_ad9680_cpack/fifo_wr_data_${k}
ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2 }
ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3 }
ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3
ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn

2
projects/fmcadc4/zc706/Makefile
View File

@ -22,7 +22,7 @@ LIB_DEPS += axi_spdif_tx
LIB_DEPS += jesd204/axi_jesd204_rx LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += util_bsplit LIB_DEPS += util_bsplit
LIB_DEPS += util_cpack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adcfifo LIB_DEPS += xilinx/axi_adcfifo
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr