From 1d4b92190aab3ed96cbde543a14ca162f7b14fb5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 19 Apr 2017 13:54:03 +0300
Subject: [PATCH] fmcomms2/zc702: Fix Warning[Synth 8-2611]

In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
---
 projects/fmcomms2/zc702/system_top.v | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v
index 57b279928..15d597244 100644
--- a/projects/fmcomms2/zc702/system_top.v
+++ b/projects/fmcomms2/zc702/system_top.v
@@ -117,10 +117,6 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
-  wire            spi_udc_csn_tx;
-  wire            spi_udc_csn_rx;
-  wire            spi_udc_sclk;
-  wire            spi_udc_data;
   wire            tdd_sync_t;
   wire            tdd_sync_o;
   wire            tdd_sync_i;