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ad9265: Initial commit

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Adrian Costina 2014-09-23 22:51:42 -04:00
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commit 1d4bc47cea
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9265 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [15:0] adc_data;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [15:0] adc_data_s;
wire adc_or_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:1];
wire up_ack_s[0:1];
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s;
up_status_pn_oos <= up_status_pn_oos_s;
up_status_or <= up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_ack <= up_ack_s[0] | up_ack_s[1];
end
end
// channel
axi_ad9265_channel #(
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_dcfilter_data_out (adc_data),
.adc_enable (adc_enable),
.adc_valid (adc_valid),
.up_adc_pn_err (up_status_pn_err_s),
.up_adc_pn_oos (up_status_pn_oos_s),
.up_adc_or (up_status_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
// main (device interface)
axi_ad9265_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9265_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dcfilter_data_out,
adc_valid,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
output adc_valid;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire [15:0] adc_dfmt_data_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
axi_ad9265_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dfmt_data_s = adc_data;
end else begin
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_dfmt_data_s),
.valid_out (adc_valid),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
`timescale 1ns/100ps
module axi_ad9265_if (
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
adc_status,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
output adc_status;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or = 'd0;
reg [ 8:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[8:0];
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
always @(posedge adc_clk)
begin
adc_status <= 1'b1;
adc_or <= adc_or_p_s | adc_or_n_s;
adc_data <= { adc_data_p_s[7], adc_data_n_s[7], adc_data_p_s[6], adc_data_n_s[6], adc_data_p_s[5], adc_data_n_s[5], adc_data_p_s[4], adc_data_n_s[4], adc_data_p_s[3], adc_data_n_s[3], adc_data_p_s[2], adc_data_n_s[2], adc_data_p_s[1], adc_data_n_s[1], adc_data_p_s[0], adc_data_n_s[0]};
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h08: delay_ld <= 15'h0100;
8'h07: delay_ld <= 15'h0080;
8'h06: delay_ld <= 15'h0040;
8'h05: delay_ld <= 15'h0020;
8'h04: delay_ld <= 15'h0010;
8'h03: delay_ld <= 15'h0008;
8'h02: delay_ld <= 15'h0004;
8'h01: delay_ld <= 15'h0002;
8'h00: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h08: delay_rdata <= delay_rdata_s[8];
8'h07: delay_rdata <= delay_rdata_s[7];
8'h06: delay_rdata <= delay_rdata_s[6];
8'h05: delay_rdata <= delay_rdata_s[5];
8'h04: delay_rdata <= delay_rdata_s[4];
8'h03: delay_rdata <= delay_rdata_s[3];
8'h02: delay_rdata <= delay_rdata_s[2];
8'h01: delay_rdata <= delay_rdata_s[1];
8'h00: delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[8]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[8]),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9265
adi_ip_files axi_ad9265 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_lvds_clk.v" \
"$ad_hdl_dir/library/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad9265_pnmon.v" \
"axi_ad9265_if.v" \
"axi_ad9265_channel.v" \
"axi_ad9265.v"]
adi_ip_properties axi_ad9265
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9265_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
// internal registers
reg adc_valid_in = 'd0;
reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0;
// internal signals
wire [31:0] adc_pn_data_pn_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_valid_in <= ~adc_valid_in;
adc_pn_data_in <= {adc_pn_data_in[15:0], adc_data[15:0]};
if(adc_valid_in == 1'b1) begin
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ad9265
set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p]
set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n]
set adc_data_or_p [create_bd_port -dir I adc_data_or_p]
set adc_data_or_n [create_bd_port -dir I adc_data_or_n]
set adc_data_in_n [create_bd_port -dir I -from 7 -to 0 adc_data_in_n]
set adc_data_in_p [create_bd_port -dir I -from 7 -to 0 adc_data_in_p]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_csn0 [create_bd_port -dir O spi_csn0]
set spi_csn1 [create_bd_port -dir O spi_csn1]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set gnd [create_bd_port -dir I gnd]
set vdd [create_bd_port -dir I vdd]
# adc peripheral
set axi_ad9265 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9265:1.0 axi_ad9265]
set axi_ad9265_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9265_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma
if {$sys_zynq == 1} {
set axi_ad9265_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9265_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9265_dma_interconnect
}
# spi
if {$sys_zynq == 0} {
set axi_ad9265_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9265_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9265_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9265_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9265_spi
} else {
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
}
# additions to default configuration
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_MI {10}] $axi_cpu_interconnect
} else {
set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
}
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc
set_property -dict [list CONFIG.NUM_SI {9}] $axi_mem_interconnect
}
# clock for ila
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
set_property LEFT 31 [get_bd_ports GPIO_I]
set_property LEFT 31 [get_bd_ports GPIO_O]
set_property LEFT 31 [get_bd_ports GPIO_T]
set sys_ila_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_ila_clk $sys_ila_clk_source
} else {
set ila_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 ila_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200}] $ila_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $ila_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $ila_clkgen
set_property -dict [list CONFIG.USE_RESET {false}] $ila_clkgen
connect_bd_net -net sys_200m_clk [get_bd_pins ila_clkgen/clk_in1]
set sys_ila_clk_source [get_bd_pins ila_clkgen/clk_out1]
connect_bd_net -net sys_ila_clk $sys_ila_clk_source
}
# connections (spi)
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9265_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9265_spi/ss_o]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9265_spi/sck_i]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9265_spi/sck_o]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9265_spi/io0_i]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9265_spi/io0_o]
connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9265_spi/io1_i]
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
delete_bd_objs [get_bd_ports unc_int2]
} else {
connect_bd_net -net spi_csn0 [get_bd_ports spi_csn0] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn1 [get_bd_ports spi_csn1] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
}
# connections (ad9265)
connect_bd_net -net axi_ad9265_adc_clk_in_n [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9265/adc_clk_in_p]
connect_bd_net -net axi_ad9265_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9265/adc_clk_in_n]
connect_bd_net -net axi_ad9265_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9265/adc_data_in_n]
connect_bd_net -net axi_ad9265_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9265/adc_data_in_p]
connect_bd_net -net axi_ad9265_adc_data_or_p [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9265/adc_or_in_p]
connect_bd_net -net axi_ad9265_adc_data_or_n [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9265/adc_or_in_n]
set adc_125m_clk_source [get_bd_pins axi_ad9265/adc_clk]
connect_bd_net -net adc_125m_clk [get_bd_pins axi_ad9265_dma/fifo_wr_clk] $adc_125m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265/delay_clk]
connect_bd_net -net axi_ad9265_dma_valid [get_bd_pins axi_ad9265/adc_valid] [get_bd_pins axi_ad9265_dma/fifo_wr_en]
connect_bd_net -net axi_ad9265_dma_data [get_bd_pins axi_ad9265/adc_data] [get_bd_pins axi_ad9265_dma/fifo_wr_din]
connect_bd_net -net axi_ad9265_dma_dovf [get_bd_pins axi_ad9265/adc_dovf] [get_bd_pins axi_ad9265_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins $sys_100m_clk_source]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins $sys_100m_clk_source]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] [get_bd_pins $sys_100m_resetn_source]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] [get_bd_pins $sys_100m_resetn_source]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma/s_axi_aresetn]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9265_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9265/s_axi]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9265_spi/axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_spi/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_spi/s_axi_aresetn]
connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
}
# interconnect (mem/adc)
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9265_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9265_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_ad9265_dma_interconnect_s0 [get_bd_intf_pins axi_ad9265_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9265_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9265_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9265_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma_interconnect/S00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma_interconnect/ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9265_dma_interconnect/M00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
}
# ila (with fifo to prevent timing failure)
set ila_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 ila_fifo]
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_fifo
set_property -dict [list CONFIG.Input_Data_Width {16}] $ila_fifo
set_property -dict [list CONFIG.Input_Depth {128}] $ila_fifo
set_property -dict [list CONFIG.Output_Data_Width {32}] $ila_fifo
set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_fifo
set_property -dict [list CONFIG.Reset_Pin {false}] $ila_fifo
set ila_ad9265_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_ad9265_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9265_mon
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9265_mon
connect_bd_net -net axi_ad9265_dma_data [get_bd_pins ila_fifo/din] [get_bd_pins axi_ad9265/adc_data]
connect_bd_net -net adc_125m_clk [get_bd_pins axi_ad9265/adc_clk] [get_bd_pins ila_fifo/wr_clk]
connect_bd_net -net sys_ila_clk [get_bd_pins ila_fifo/rd_clk] [get_bd_pins ila_ad9265_mon/clk]
connect_bd_net -net vdd [get_bd_pins ila_fifo/rd_en] [get_bd_pins ila_fifo/wr_en] [get_bd_ports vdd]
connect_bd_net -net ila_fifo_dout [get_bd_pins ila_fifo/dout] [get_bd_pins ila_ad9265_mon/probe0]
# address mapping
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9265/s_axi/axi_lite] SEG_data_ad9265_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9265_dma/s_axi/axi_lite] SEG_data_ad9265_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9265_spi/axi_lite/Reg] SEG_data_ad9265_spi
}
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9265_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9265_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
}

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9265_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 1:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz: spi_mosi;
assign spi_miso = spi_sdio;
endmodule

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad9265_bd.tcl

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# ad9265
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ;
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ;
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p] ;
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n] ;
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ;
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ;
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ;
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ;
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ;
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ;
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ;
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ;
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ;
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ;
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ;
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ;
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ;
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ;
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ;
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ;
## spi
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ;
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ;
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25} [get_ports spi_clk] ;
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ;
# clocks
create_clock -name adc_clk -period 3.33 [get_ports adc_clk_in_p]
create_clock -name ila_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {adc_clk}
set_clock_groups -asynchronous -group {ila_clk}

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# load script
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
set project_name ad9265_fmc_zc706
adi_project_create $project_name
adi_project_files $project_name [list "../common/ad9265_spi.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
adi_project_run $project_name

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
adc_clk_in_n,
adc_clk_in_p,
adc_data_in_n,
adc_data_in_p,
adc_data_or_n,
adc_data_or_p,
spi_clk,
spi_csn_adc,
spi_csn_clk,
spi_sdio
);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input adc_clk_in_n;
input adc_clk_in_p;
input [ 7:0] adc_data_in_n;
input [ 7:0] adc_data_in_p;
input adc_data_or_n;
input adc_data_or_p;
output spi_clk;
output spi_csn_adc;
output spi_csn_clk;
inout spi_sdio;
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) iobuf_gpio_bd (
.di (gpio_o),
.do (gpio_i),
.dt (gpio_t),
.dio (gpio_bd));
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9265_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
system_wrapper i_system_wrapper (
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.vdd(1'b1),
.gnd(1'b0),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn0(spi_csn[0]),
.spi_csn1(spi_csn[1]),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************