pzsdr/ccbrk: loopback board support
Rejeesh Kutty
parent
e7fd964874
commit
1d6254fdec
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@ -1,107 +1,259 @@
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# constraints
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# loopback
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk0_p] ; ## IO_L13P_T2_MRCC_12
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk0_n] ; ## IO_L13N_T2_MRCC_12
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set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk1_p] ; ## IO_L13P_T2_MRCC_13
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set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk1_n] ; ## IO_L13N_T2_MRCC_13
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## p4
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports fmc_prstn] ; ## IO_25_13
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set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[0]] ; ## IO_L12P_T1_MRCC_12
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[0]] ; ## IO_L12N_T1_MRCC_12
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[1]] ; ## IO_L11P_T1_SRCC_12
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set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[1]] ; ## IO_L11N_T1_SRCC_12
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set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[2]] ; ## IO_L1P_T0_12
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set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[2]] ; ## IO_L1N_T0_12
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set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[3]] ; ## IO_L2P_T0_12
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set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[3]] ; ## IO_L2N_T0_12
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[4]] ; ## IO_L3P_T0_DQS_12
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set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[4]] ; ## IO_L3N_T0_DQS_12
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set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[5]] ; ## IO_L4P_T0_12
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set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[5]] ; ## IO_L4N_T0_12
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set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[6]] ; ## IO_L5P_T0_12
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set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[6]] ; ## IO_L5N_T0_12
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set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[7]] ; ## IO_L6P_T0_12
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[7]] ; ## IO_L6N_T0_VREF_12
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set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[8]] ; ## IO_L7P_T1_12
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set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[8]] ; ## IO_L7N_T1_12
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[9]] ; ## IO_L8P_T1_12
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[9]] ; ## IO_L8N_T1_12
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set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[10]] ; ## IO_L9P_T1_DQS_12
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set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[10]] ; ## IO_L9N_T1_DQS_12
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[11]] ; ## IO_L10P_T1_12
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[11]] ; ## IO_L10N_T1_12
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set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[12]] ; ## IO_L14P_T2_SRCC_12
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set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[12]] ; ## IO_L14N_T2_SRCC_12
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set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[13]] ; ## IO_L15P_T2_DQS_12
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set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[13]] ; ## IO_L15N_T2_DQS_12
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[14]] ; ## IO_L16P_T2_12
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set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[14]] ; ## IO_L16N_T2_12
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[15]] ; ## IO_L17P_T2_12
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[15]] ; ## IO_L17N_T2_12
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[16]] ; ## IO_L18P_T2_12
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set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[16]] ; ## IO_L18N_T2_12
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set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[17]] ; ## IO_L12P_T1_MRCC_13
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set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[17]] ; ## IO_L12N_T1_MRCC_13
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set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[18]] ; ## IO_L11P_T1_SRCC_13
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set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[18]] ; ## IO_L11N_T1_SRCC_13
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set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[19]] ; ## IO_L1P_T0_13
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set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[19]] ; ## IO_L1N_T0_13
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set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[20]] ; ## IO_L2P_T0_13
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set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[20]] ; ## IO_L2N_T0_13
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set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[21]] ; ## IO_L3P_T0_DQS_13
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set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[21]] ; ## IO_L3N_T0_DQS_13
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set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[22]] ; ## IO_L4P_T0_13
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set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[22]] ; ## IO_L4N_T0_13
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set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[23]] ; ## IO_L6P_T0_13
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set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[23]] ; ## IO_L6N_T0_VREF_13
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set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[24]] ; ## IO_L7P_T1_13
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set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[24]] ; ## IO_L7N_T1_13
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set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[25]] ; ## IO_L8P_T1_13
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set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[25]] ; ## IO_L8N_T1_13
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set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[26]] ; ## IO_L9P_T1_DQS_13
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set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[26]] ; ## IO_L9N_T1_DQS_13
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[27]] ; ## IO_L10P_T1_13
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set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[27]] ; ## IO_L10N_T1_13
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set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[28]] ; ## IO_L14P_T2_SRCC_13
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set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[28]] ; ## IO_L14N_T2_SRCC_13
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set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[29]] ; ## IO_L15P_T2_DQS_13
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[29]] ; ## IO_L15N_T2_DQS_13
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set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[30]] ; ## IO_L16P_T2_13
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set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[30]] ; ## IO_L16N_T2_13
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set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[31]] ; ## IO_L17P_T2_13
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set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[31]] ; ## IO_L17N_T2_13
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set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[32]] ; ## IO_L18P_T2_13
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set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[32]] ; ## IO_L18N_T2_13
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set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[33]] ; ## IO_L19P_T3_13
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[33]] ; ## IO_L19N_T3_VREF_13
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set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports pmod0[0]] ; ## IO_L21P_T3_DQS_13
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports pmod0[1]] ; ## IO_L21N_T3_DQS_13
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports pmod0[2]] ; ## IO_L22P_T3_13
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports pmod0[3]] ; ## IO_L22N_T3_13
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set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports pmod0[4]] ; ## IO_L23P_T3_13
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports pmod0[5]] ; ## IO_L23N_T3_13
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports pmod0[6]] ; ## IO_L24P_T3_13
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set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports pmod0[7]] ; ## IO_L24N_T3_13
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports pmod1[0]] ; ## IO_L19P_T3_34
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set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports pmod1[1]] ; ## IO_L19N_T3_VREF_34
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports pmod1[2]] ; ## IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports pmod1[3]] ; ## IO_L20N_T3_34
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set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports pmod1[4]] ; ## IO_L21P_T3_DQS_34
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports pmod1[5]] ; ## IO_L21N_T3_DQS_34
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set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports pmod1[6]] ; ## IO_L22P_T3_34
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set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports pmod1[7]] ; ## IO_L22N_T3_34
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set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## IO_L2P_T0_33
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set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_in[0]] ; ## IO_L1P_T0_33
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set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports gp_out[1]] ; ## IO_L2N_T0_33
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_in[1]] ; ## IO_L1N_T0_33
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set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports gp_out[2]] ; ## IO_L4P_T0_33
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set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports gp_in[2]] ; ## IO_L3P_T0_DQS_33
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set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18} [get_ports gp_out[3]] ; ## IO_L4N_T0_33
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set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports gp_in[3]] ; ## IO_L3N_T0_DQS_33
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set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18} [get_ports gp_out[4]] ; ## IO_L6P_T0_33
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports gp_in[4]] ; ## IO_L5P_T0_33
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports gp_out[5]] ; ## IO_L6N_T0_VREF_33
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set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports gp_in[5]] ; ## IO_L5N_T0_33
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set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports gp_out[6]] ; ## IO_L8P_T1_33
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set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports gp_in[6]] ; ## IO_L7P_T1_33
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set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports gp_out[7]] ; ## IO_L8N_T1_33
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set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18} [get_ports gp_in[7]] ; ## IO_L7N_T1_33
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set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18} [get_ports gp_out[8]] ; ## IO_L10P_T1_33
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set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports gp_in[8]] ; ## IO_L9P_T1_DQS_33
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set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18} [get_ports gp_out[9]] ; ## IO_L10N_T1_33
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set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports gp_in[9]] ; ## IO_L9N_T1_DQS_33
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set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_out[10]] ; ## IO_L12P_T1_MRCC_33
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set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports gp_in[10]] ; ## IO_L11P_T1_SRCC_33
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set_property -dict {PACKAGE_PIN W6} [get_ports fmc_gt_ref_clk_p] ; ## MGTREFCLK0P_111
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set_property -dict {PACKAGE_PIN W5} [get_ports fmc_gt_ref_clk_n] ; ## MGTREFCLK0N_111
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set_property -dict {PACKAGE_PIN AF8} [get_ports fmc_gt_tx_p] ; ## MGTXTXP0_111
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set_property -dict {PACKAGE_PIN AF7} [get_ports fmc_gt_tx_n] ; ## MGTXTXN0_111
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set_property -dict {PACKAGE_PIN AD8} [get_ports fmc_gt_rx_p] ; ## MGTXRXP0_111
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set_property -dict {PACKAGE_PIN AD7} [get_ports fmc_gt_rx_n] ; ## MGTXRXN0_111
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## p5
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# clocks
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set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[11]] ; ## IO_L17P_T2_33
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set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_in[11]] ; ## IO_L16P_T2_33
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set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[12]] ; ## IO_L17N_T2_33
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set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_in[12]] ; ## IO_L16N_T2_33
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set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[13]] ; ## IO_L19P_T3_33
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set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_in[13]] ; ## IO_L18P_T2_33
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set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[14]] ; ## IO_L19N_T3_VREF_33
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set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_in[14]] ; ## IO_L18N_T2_33
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set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_out[15]] ; ## IO_L20P_T3_33
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set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_in[15]] ; ## IO_L21P_T3_DQS_33
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set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_out[16]] ; ## IO_L20N_T3_33
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set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_in[16]] ; ## IO_L21N_T3_DQS_33
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set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_out[17]] ; ## IO_L22P_T3_33
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set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[17]] ; ## IO_L23P_T3_33
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set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_out[18]] ; ## IO_L22N_T3_33
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set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[18]] ; ## IO_L23N_T3_33
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set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gp_out[19]] ; ## IO_25_VRP_34
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set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports gp_in[19]] ; ## IO_L10N_T1_34
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set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[20]] ; ## IO_L14P_T2_SRCC_33
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set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_in[20]] ; ## IO_L24P_T3_33
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set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[21]] ; ## IO_L14N_T2_SRCC_33
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set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_in[21]] ; ## IO_L24N_T3_33
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set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## IO_L13P_T2_MRCC_33
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set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## IO_L15P_T2_DQS_33
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set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## IO_L13N_T2_MRCC_33
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set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## IO_L15N_T2_DQS_33
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create_clock -name ref_clk -period 4.00 [get_ports fmc_gt_ref_clk_p]
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## p6
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set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## IO_L2P_T0_34
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## IO_L1P_T0_34
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set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## IO_L2N_T0_34
|
||||
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## IO_L1N_T0_34
|
||||
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## IO_L4P_T0_34
|
||||
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## IO_L3P_T0_DQS_PUDC_B_34
|
||||
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## IO_L4N_T0_34
|
||||
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## IO_L3N_T0_DQS_34
|
||||
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports gp_out[28]] ; ## IO_L6P_T0_34
|
||||
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_in[28]] ; ## IO_L5P_T0_34
|
||||
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gp_out[29]] ; ## IO_L6N_T0_VREF_34
|
||||
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gp_in[29]] ; ## IO_L5N_T0_34
|
||||
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gp_out[30]] ; ## IO_L8P_T1_34
|
||||
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gp_in[30]] ; ## IO_L7P_T1_34
|
||||
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports gp_out[31]] ; ## IO_L12P_T1_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports gp_in[31]] ; ## IO_L11P_T1_SRCC_34
|
||||
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports gp_out[32]] ; ## IO_L12N_T1_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports gp_in[32]] ; ## IO_L11N_T1_SRCC_34
|
||||
|
||||
## p7
|
||||
|
||||
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports gp_out[33]] ; ## IO_L14P_T2_SRCC_34
|
||||
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports gp_in[33]] ; ## IO_L13P_T2_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports gp_out[34]] ; ## IO_L14N_T2_SRCC_34
|
||||
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports gp_in[34]] ; ## IO_L13N_T2_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports gp_out[35]] ; ## IO_L16P_T2_34
|
||||
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports gp_in[35]] ; ## IO_L15P_T2_DQS_34
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports gp_out[36]] ; ## IO_L16N_T2_34
|
||||
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports gp_in[36]] ; ## IO_L15N_T2_DQS_34
|
||||
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## IO_L20P_T3_34
|
||||
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L19P_T3_34
|
||||
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## IO_L20N_T3_34
|
||||
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L19N_T3_VREF_34
|
||||
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## IO_L22P_T3_34
|
||||
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## IO_L21P_T3_DQS_34
|
||||
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## IO_L22N_T3_34
|
||||
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## IO_L21N_T3_DQS_34
|
||||
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## IO_0_VRN_33
|
||||
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## IO_L18P_T2_34
|
||||
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## IO_25_VRP_33
|
||||
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## IO_L18N_T2_34
|
||||
|
||||
## p13
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[43]] ; ## IO_L16P_T2_12
|
||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_in[43]] ; ## IO_L15P_T2_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[44]] ; ## IO_L16N_T2_12
|
||||
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_in[44]] ; ## IO_L15N_T2_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[45]] ; ## IO_L14P_T2_SRCC_12
|
||||
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports gp_in[45]] ; ## IO_L13P_T2_MRCC_12
|
||||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[46]] ; ## IO_L14N_T2_SRCC_12
|
||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gp_in[46]] ; ## IO_L13N_T2_MRCC_12
|
||||
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[47]] ; ## IO_L12P_T1_MRCC_12
|
||||
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_in[47]] ; ## IO_L11P_T1_SRCC_12
|
||||
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[48]] ; ## IO_L12N_T1_MRCC_12
|
||||
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_in[48]] ; ## IO_L11N_T1_SRCC_12
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[49]] ; ## IO_L10P_T1_12
|
||||
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_in[49]] ; ## IO_L9P_T1_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[50]] ; ## IO_L10N_T1_12
|
||||
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_in[50]] ; ## IO_L9N_T1_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[51]] ; ## IO_L8P_T1_12
|
||||
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_in[51]] ; ## IO_L7P_T1_12
|
||||
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[52]] ; ## IO_L8N_T1_12
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_in[52]] ; ## IO_L7N_T1_12
|
||||
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[53]] ; ## IO_L6P_T0_12
|
||||
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_in[53]] ; ## IO_L5P_T0_12
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[54]] ; ## IO_L6N_T0_VREF_12
|
||||
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_in[54]] ; ## IO_L5N_T0_12
|
||||
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[55]] ; ## IO_L4P_T0_12
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_in[55]] ; ## IO_L3P_T0_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[56]] ; ## IO_L4N_T0_12
|
||||
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_in[56]] ; ## IO_L3N_T0_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[57]] ; ## IO_L2P_T0_12
|
||||
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_in[57]] ; ## IO_L1P_T0_12
|
||||
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[58]] ; ## IO_L2N_T0_12
|
||||
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_in[58]] ; ## IO_L1N_T0_12
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[59]] ; ## IO_L18P_T2_12
|
||||
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_in[59]] ; ## IO_L17P_T2_12
|
||||
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[60]] ; ## IO_L18N_T2_12
|
||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_in[60]] ; ## IO_L17N_T2_12
|
||||
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_out[61]] ; ## IO_L20P_T3_12
|
||||
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_in[61]] ; ## IO_L19P_T3_12
|
||||
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_out[62]] ; ## IO_L20N_T3_12
|
||||
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_in[62]] ; ## IO_L19N_T3_VREF_12
|
||||
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_out[63]] ; ## IO_L22P_T3_12
|
||||
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_in[63]] ; ## IO_L21P_T3_DQS_12
|
||||
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gp_out[64]] ; ## IO_L22N_T3_12
|
||||
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_in[64]] ; ## IO_L21N_T3_DQS_12
|
||||
|
||||
## p2
|
||||
|
||||
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_out[65]] ; ## IO_25_13
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[65]] ; ## IO_L6P_T0_13
|
||||
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_out[66]] ; ## IO_L2P_T0_13
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[66]] ; ## IO_L1P_T0_13
|
||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_out[67]] ; ## IO_L2N_T0_13
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[67]] ; ## IO_L1N_T0_13
|
||||
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_out[68]] ; ## IO_L4P_T0_13
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[68]] ; ## IO_L3P_T0_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_out[69]] ; ## IO_L4N_T0_13
|
||||
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[69]] ; ## IO_L3N_T0_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_out[70]] ; ## IO_L8P_T1_13
|
||||
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[70]] ; ## IO_L7P_T1_13
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_out[71]] ; ## IO_L8N_T1_13
|
||||
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[71]] ; ## IO_L7N_T1_13
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_out[72]] ; ## IO_L10P_T1_13
|
||||
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[72]] ; ## IO_L9P_T1_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_out[73]] ; ## IO_L10N_T1_13
|
||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[73]] ; ## IO_L9N_T1_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_out[74]] ; ## IO_L12P_T1_MRCC_13
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[74]] ; ## IO_L11P_T1_SRCC_13
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_out[75]] ; ## IO_L12N_T1_MRCC_13
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[75]] ; ## IO_L11N_T1_SRCC_13
|
||||
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_out[76]] ; ## IO_L14P_T2_SRCC_13
|
||||
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports gp_in[76]] ; ## IO_L13P_T2_MRCC_13
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_out[77]] ; ## IO_L14N_T2_SRCC_13
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports gp_in[77]] ; ## IO_L13N_T2_MRCC_13
|
||||
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_out[78]] ; ## IO_L16P_T2_13
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[78]] ; ## IO_L15P_T2_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_out[79]] ; ## IO_L16N_T2_13
|
||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[79]] ; ## IO_L15N_T2_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_out[80]] ; ## IO_L18P_T2_13
|
||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[80]] ; ## IO_L17P_T2_13
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_out[81]] ; ## IO_L18N_T2_13
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[81]] ; ## IO_L17N_T2_13
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gp_out[82]] ; ## IO_L20P_T3_13
|
||||
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[82]] ; ## IO_L19P_T3_13
|
||||
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gp_out[83]] ; ## IO_L20N_T3_13
|
||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[83]] ; ## IO_L19N_T3_VREF_13
|
||||
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[84]] ; ## IO_L22P_T3_13
|
||||
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_in[84]] ; ## IO_L21P_T3_DQS_13
|
||||
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[85]] ; ## IO_L22N_T3_13
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in[85]] ; ## IO_L21N_T3_DQS_13
|
||||
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_out[86]] ; ## IO_L24P_T3_13
|
||||
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[86]] ; ## IO_L23P_T3_13
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_out[87]] ; ## IO_L24N_T3_13
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_in[87]] ; ## IO_L23N_T3_13
|
||||
|
||||
## vcc
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L6N_T0_VREF_13
|
||||
|
||||
## on board
|
||||
|
||||
set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111
|
||||
set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111
|
||||
set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111
|
||||
set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111
|
||||
set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111
|
||||
set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111
|
||||
set_property -dict {PACKAGE_PIN AC6} [get_ports gt_rx_p[2]] ; ## MGTXRXP2_111
|
||||
set_property -dict {PACKAGE_PIN AC5} [get_ports gt_rx_n[2]] ; ## MGTXRXN2_111
|
||||
set_property -dict {PACKAGE_PIN AD4} [get_ports gt_rx_p[3]] ; ## MGTXRXP3_111
|
||||
set_property -dict {PACKAGE_PIN AD3} [get_ports gt_rx_n[3]] ; ## MGTXRXN3_111
|
||||
set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111
|
||||
set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111
|
||||
set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111
|
||||
set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111
|
||||
set_property -dict {PACKAGE_PIN AE2} [get_ports gt_tx_p[2]] ; ## MGTXTXP2_111
|
||||
set_property -dict {PACKAGE_PIN AE1} [get_ports gt_tx_n[2]] ; ## MGTXTXN2_111
|
||||
set_property -dict {PACKAGE_PIN AC2} [get_ports gt_tx_p[3]] ; ## MGTXTXP3_111
|
||||
set_property -dict {PACKAGE_PIN AC1} [get_ports gt_tx_n[3]] ; ## MGTXTXN3_111
|
||||
|
||||
## clocks
|
||||
|
||||
create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
|
||||
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
|
||||
## MIO loopbacks (fixed-io)
|
||||
## the following are connected to AD9361 GPIO
|
||||
|
||||
## JX4.86 A23 PS_MIO12_500_JX4 <==> JX4.2 NA AD9361_GPO1
|
||||
## JX4.88 B26 PS_MIO11_500_JX4 <==> JX4.1 NA AD9361_GPO0
|
||||
## JX4.91 B25 PS_MIO13_500_JX4 <==> JX4.3 NA AD9361_GPO2
|
||||
## JX4.93 D23 PS_MIO14_500_JX4 <==> JX4.4 NA AD9361_GPO3
|
||||
|
||||
## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
|
||||
|
||||
## JX4.92 E17 PS_MIO46_501_JX4 <==> JX4.94 B19 PS_MIO47_501_JX4
|
||||
|
||||
## the following are mio-to-pl loopback
|
||||
|
||||
## JX4.97 E26 PS_MIO00_500_JX4 <==> JX1.76 K3 IO_L11N_T1_SRCC_33
|
||||
## JX4.100 B20 PS_MIO51_501_JX4 <==> JX4.67 A9 IO_L17P_T2_34
|
||||
## JX4.85 C24 PS_MIO15_500_JX4 <==> JX4.37 E5 IO_L7N_T1_34
|
||||
## JX4.87 A25 PS_MIO10_500_JX4 <==> JX4.42 E6 IO_L10P_T1_34
|
||||
|
||||
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[0]] ; ## IO_L11N_T1_SRCC_33
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[1]] ; ## IO_L17P_T2_34
|
||||
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[2]] ; ## IO_L7N_T1_34
|
||||
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[3]] ; ## IO_L10P_T1_34
|
||||
|
||||
|
|
|
|||
|
|
@ -95,22 +95,17 @@ module system_top (
|
|||
spi_mosi,
|
||||
spi_miso,
|
||||
|
||||
fmc_prstn,
|
||||
fmc_clk0_p,
|
||||
fmc_clk0_n,
|
||||
fmc_clk1_p,
|
||||
fmc_clk1_n,
|
||||
fmc_la_p,
|
||||
fmc_la_n,
|
||||
pmod0,
|
||||
pmod1,
|
||||
gp_out,
|
||||
gp_in,
|
||||
gp_in_mio,
|
||||
gp_in_1,
|
||||
|
||||
fmc_gt_ref_clk_p,
|
||||
fmc_gt_ref_clk_n,
|
||||
fmc_gt_tx_p,
|
||||
fmc_gt_tx_n,
|
||||
fmc_gt_rx_p,
|
||||
fmc_gt_rx_n);
|
||||
gt_ref_clk_p,
|
||||
gt_ref_clk_n,
|
||||
gt_tx_p,
|
||||
gt_tx_n,
|
||||
gt_rx_p,
|
||||
gt_rx_n);
|
||||
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
|
|
@ -168,132 +163,45 @@ module system_top (
|
|||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
input fmc_prstn;
|
||||
input fmc_clk0_p;
|
||||
input fmc_clk0_n;
|
||||
input fmc_clk1_p;
|
||||
input fmc_clk1_n;
|
||||
inout [33:0] fmc_la_p;
|
||||
inout [33:0] fmc_la_n;
|
||||
inout [ 7:0] pmod0;
|
||||
inout [ 7:0] pmod1;
|
||||
output [87:0] gp_out;
|
||||
input [87:0] gp_in;
|
||||
input [ 3:0] gp_in_mio;
|
||||
input gp_in_1;
|
||||
|
||||
input fmc_gt_ref_clk_p;
|
||||
input fmc_gt_ref_clk_n;
|
||||
output fmc_gt_tx_p;
|
||||
output fmc_gt_tx_n;
|
||||
input fmc_gt_rx_p;
|
||||
input fmc_gt_rx_n;
|
||||
input gt_ref_clk_p;
|
||||
input gt_ref_clk_n;
|
||||
output [ 3:0] gt_tx_p;
|
||||
output [ 3:0] gt_tx_n;
|
||||
input [ 3:0] gt_rx_p;
|
||||
input [ 3:0] gt_rx_n;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire fmc_clk0_s;
|
||||
wire fmc_clk0;
|
||||
wire [31:0] up_clk0_count;
|
||||
wire fmc_clk1_s;
|
||||
wire fmc_clk1;
|
||||
wire [31:0] up_clk1_count;
|
||||
wire fmc_gt_ref_clk;
|
||||
wire [31:0] gpio_0_0_i;
|
||||
wire [31:0] gpio_0_0_o;
|
||||
wire [31:0] gpio_0_0_t;
|
||||
wire [31:0] gpio_0_1_i;
|
||||
wire [31:0] gpio_0_1_o;
|
||||
wire [31:0] gpio_0_1_t;
|
||||
wire [31:0] gpio_1_0_i;
|
||||
wire [31:0] gpio_1_0_o;
|
||||
wire [31:0] gpio_1_0_t;
|
||||
wire [31:0] gpio_1_1_i;
|
||||
wire [31:0] gpio_1_1_o;
|
||||
wire [31:0] gpio_1_1_t;
|
||||
wire [31:0] gpio_3_1_o;
|
||||
wire gt_ref_clk;
|
||||
wire [95:0] gp_out_s;
|
||||
wire [95:0] gp_in_s;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire up_clk;
|
||||
wire up_rst;
|
||||
wire up_rstn;
|
||||
wire up_pn_err_clr;
|
||||
wire up_pn_oos_clr;
|
||||
wire up_pn_err;
|
||||
wire up_pn_oos;
|
||||
|
||||
// assignments
|
||||
|
||||
assign gp_out = gp_out_s[87:0];
|
||||
|
||||
assign gp_in_s[95:93] = 3'd0;
|
||||
assign gp_in_s[92:92] = gp_in_1;
|
||||
assign gp_in_s[91:88] = gp_in_mio;
|
||||
assign gp_in_s[87: 0] = gp_in;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS i_ibufds_clk0 (
|
||||
.I (fmc_clk0_p),
|
||||
.IB (fmc_clk0_n),
|
||||
.O (fmc_clk0_s));
|
||||
|
||||
BUFG i_bufg_clk0 (
|
||||
.I (fmc_clk0_s),
|
||||
.O (fmc_clk0));
|
||||
|
||||
up_clock_mon i_clk0_mon (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_d_count (up_clk0_count),
|
||||
.d_rst (up_rst),
|
||||
.d_clk (fmc_clk0));
|
||||
|
||||
IBUFDS i_ibufds_clk1 (
|
||||
.I (fmc_clk1_p),
|
||||
.IB (fmc_clk1_n),
|
||||
.O (fmc_clk1_s));
|
||||
|
||||
BUFG i_bufg_clk1 (
|
||||
.I (fmc_clk1_s),
|
||||
.O (fmc_clk1));
|
||||
|
||||
up_clock_mon i_clk1_mon (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_d_count (up_clk1_count),
|
||||
.d_rst (up_rst),
|
||||
.d_clk (fmc_clk1));
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_ref_clk (
|
||||
IBUFDS_GTE2 i_ibufds_gt_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (fmc_gt_ref_clk_p),
|
||||
.IB (fmc_gt_ref_clk_n),
|
||||
.O (fmc_gt_ref_clk),
|
||||
.I (gt_ref_clk_p),
|
||||
.IB (gt_ref_clk_n),
|
||||
.O (gt_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
assign gpio_0_1_i[31:10] = 'd0;
|
||||
assign gpio_1_1_i[31:10] = 'd0;
|
||||
assign up_pn_err_clr = gpio_3_1_o[1];
|
||||
assign up_pn_oos_clr = gpio_3_1_o[0];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod0_fmc_p (
|
||||
.dio_t ({gpio_0_1_t[9:0], gpio_0_0_t[31:0]}),
|
||||
.dio_i ({gpio_0_1_o[9:0], gpio_0_0_o[31:0]}),
|
||||
.dio_o ({gpio_0_1_i[9:0], gpio_0_0_i[31:0]}),
|
||||
.dio_p ({ pmod1[3],
|
||||
pmod1[2],
|
||||
pmod1[1],
|
||||
pmod1[0],
|
||||
pmod0[3],
|
||||
pmod0[2],
|
||||
pmod0[1],
|
||||
pmod0[0],
|
||||
fmc_la_n[16:0],
|
||||
fmc_la_p[16:0]}));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod1_fmc_n (
|
||||
.dio_t ({gpio_1_1_t[9:0], gpio_1_0_t[31:0]}),
|
||||
.dio_i ({gpio_1_1_o[9:0], gpio_1_0_o[31:0]}),
|
||||
.dio_o ({gpio_1_1_i[9:0], gpio_1_0_i[31:0]}),
|
||||
.dio_p ({ pmod1[7],
|
||||
pmod1[6],
|
||||
pmod1[5],
|
||||
pmod1[4],
|
||||
pmod0[7],
|
||||
pmod0[6],
|
||||
pmod0[5],
|
||||
pmod0[4],
|
||||
fmc_la_n[33:17],
|
||||
fmc_la_p[33:17]}));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
|
||||
.dio_t ({gpio_t[51], gpio_t[46:32]}),
|
||||
.dio_i ({gpio_o[51], gpio_o[46:32]}),
|
||||
|
|
@ -334,39 +242,32 @@ module system_top (
|
|||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.fmc_gt_ref_clk0 (fmc_gt_ref_clk),
|
||||
.fmc_gt_ref_clk1 (fmc_gt_ref_clk),
|
||||
.fmc_gt_rx_n (fmc_gt_rx_n),
|
||||
.fmc_gt_rx_p (fmc_gt_rx_p),
|
||||
.fmc_gt_tx_n (fmc_gt_tx_n),
|
||||
.fmc_gt_tx_p (fmc_gt_tx_p),
|
||||
.gpio_0_0_i (gpio_0_0_i),
|
||||
.gpio_0_0_o (gpio_0_0_o),
|
||||
.gpio_0_0_t (gpio_0_0_t),
|
||||
.gpio_0_1_i (gpio_0_1_i),
|
||||
.gpio_0_1_o (gpio_0_1_o),
|
||||
.gpio_0_1_t (gpio_0_1_t),
|
||||
.gpio_1_0_i (gpio_1_0_i),
|
||||
.gpio_1_0_o (gpio_1_0_o),
|
||||
.gpio_1_0_t (gpio_1_0_t),
|
||||
.gpio_1_1_i (gpio_1_1_i),
|
||||
.gpio_1_1_o (gpio_1_1_o),
|
||||
.gpio_1_1_t (gpio_1_1_t),
|
||||
.gpio_2_0_i (up_clk0_count),
|
||||
.gpio_2_0_o (),
|
||||
.gpio_2_0_t (),
|
||||
.gpio_2_1_i (up_clk1_count),
|
||||
.gpio_2_1_o (),
|
||||
.gpio_2_1_t (),
|
||||
.gpio_3_0_i ({31'd0, fmc_prstn}),
|
||||
.gpio_3_0_o (),
|
||||
.gpio_3_0_t (),
|
||||
.gpio_3_1_i ({30'd0, up_pn_err, up_pn_oos}),
|
||||
.gpio_3_1_o (gpio_3_1_o),
|
||||
.gpio_3_1_t (),
|
||||
.gp_in_0 (gp_in_s[31:0]),
|
||||
.gp_in_1 (gp_in_s[63:32]),
|
||||
.gp_in_2 (gp_in_s[95:64]),
|
||||
.gp_out_0 (gp_out_s[31:0]),
|
||||
.gp_out_1 (gp_out_s[63:32]),
|
||||
.gp_out_2 (gp_out_s[95:64]),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.gt_ref_clk (gt_ref_clk),
|
||||
.gt_rx_0_n (gt_rx_n[0]),
|
||||
.gt_rx_0_p (gt_rx_p[0]),
|
||||
.gt_rx_1_n (gt_rx_n[1]),
|
||||
.gt_rx_1_p (gt_rx_p[1]),
|
||||
.gt_rx_2_n (gt_rx_n[2]),
|
||||
.gt_rx_2_p (gt_rx_p[2]),
|
||||
.gt_rx_3_n (gt_rx_n[3]),
|
||||
.gt_rx_3_p (gt_rx_p[3]),
|
||||
.gt_tx_0_n (gt_tx_n[0]),
|
||||
.gt_tx_0_p (gt_tx_p[0]),
|
||||
.gt_tx_1_n (gt_tx_n[1]),
|
||||
.gt_tx_1_p (gt_tx_p[1]),
|
||||
.gt_tx_2_n (gt_tx_n[2]),
|
||||
.gt_tx_2_p (gt_tx_p[2]),
|
||||
.gt_tx_3_n (gt_tx_n[3]),
|
||||
.gt_tx_3_p (gt_tx_p[3]),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.otg_vbusoc (1'b0),
|
||||
|
|
@ -417,14 +318,7 @@ module system_top (
|
|||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx),
|
||||
.up_clk (up_clk),
|
||||
.up_enable (gpio_o[47]),
|
||||
.up_pn_err (up_pn_err),
|
||||
.up_pn_err_clr (up_pn_err_clr),
|
||||
.up_pn_oos (up_pn_oos),
|
||||
.up_pn_oos_clr (up_pn_oos_clr),
|
||||
.up_rst (up_rst),
|
||||
.up_rstn (up_rstn),
|
||||
.up_txnrx (gpio_o[48]));
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -4,79 +4,13 @@
|
|||
ad_connect sys_ps7/ENET1_GMII_RX_CLK GND
|
||||
ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
|
||||
|
||||
set axi_gpio_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_0
|
||||
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_0_0_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_0_0_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_0_0_t
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_0_1_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_0_1_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_0_1_t
|
||||
|
||||
ad_connect gpio_0_0_i axi_gpio_0/gpio_io_i
|
||||
ad_connect gpio_0_0_o axi_gpio_0/gpio_io_o
|
||||
ad_connect gpio_0_0_t axi_gpio_0/gpio_io_t
|
||||
ad_connect gpio_0_1_i axi_gpio_0/gpio2_io_i
|
||||
ad_connect gpio_0_1_o axi_gpio_0/gpio2_io_o
|
||||
ad_connect gpio_0_1_t axi_gpio_0/gpio2_io_t
|
||||
|
||||
set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_1
|
||||
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_1_0_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_1_0_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_1_0_t
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_1_1_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_1_1_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_1_1_t
|
||||
|
||||
ad_connect gpio_1_0_i axi_gpio_1/gpio_io_i
|
||||
ad_connect gpio_1_0_o axi_gpio_1/gpio_io_o
|
||||
ad_connect gpio_1_0_t axi_gpio_1/gpio_io_t
|
||||
ad_connect gpio_1_1_i axi_gpio_1/gpio2_io_i
|
||||
ad_connect gpio_1_1_o axi_gpio_1/gpio2_io_o
|
||||
ad_connect gpio_1_1_t axi_gpio_1/gpio2_io_t
|
||||
|
||||
set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2
|
||||
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_2_0_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_2_0_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_2_0_t
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_2_1_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_2_1_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_2_1_t
|
||||
|
||||
ad_connect gpio_2_0_i axi_gpio_2/gpio_io_i
|
||||
ad_connect gpio_2_0_o axi_gpio_2/gpio_io_o
|
||||
ad_connect gpio_2_0_t axi_gpio_2/gpio_io_t
|
||||
ad_connect gpio_2_1_i axi_gpio_2/gpio2_io_i
|
||||
ad_connect gpio_2_1_o axi_gpio_2/gpio2_io_o
|
||||
ad_connect gpio_2_1_t axi_gpio_2/gpio2_io_t
|
||||
|
||||
set axi_gpio_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_3
|
||||
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_3_0_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_3_0_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_3_0_t
|
||||
create_bd_port -dir I -from 31 -to 0 gpio_3_1_i
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_3_1_o
|
||||
create_bd_port -dir O -from 31 -to 0 gpio_3_1_t
|
||||
|
||||
ad_connect gpio_3_0_i axi_gpio_3/gpio_io_i
|
||||
ad_connect gpio_3_0_o axi_gpio_3/gpio_io_o
|
||||
ad_connect gpio_3_0_t axi_gpio_3/gpio_io_t
|
||||
ad_connect gpio_3_1_i axi_gpio_3/gpio2_io_i
|
||||
ad_connect gpio_3_1_o axi_gpio_3/gpio2_io_o
|
||||
ad_connect gpio_3_1_t axi_gpio_3/gpio2_io_t
|
||||
# un-used io (gt)
|
||||
|
||||
set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
|
||||
set_property -dict [list CONFIG.NUM_OF_LANES {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_NUM_OF_LANES {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_NUM_OF_LANES {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
|
||||
|
|
@ -87,56 +21,170 @@ set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
|
|||
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_DATA_SEL_2 {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_DATA_SEL_3 {3}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_pzslb_gt
|
||||
|
||||
set util_pzslb_gtlb [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb]
|
||||
|
||||
create_bd_port -dir I fmc_gt_ref_clk0
|
||||
create_bd_port -dir I fmc_gt_ref_clk1
|
||||
create_bd_port -dir I fmc_gt_rx_p
|
||||
create_bd_port -dir I fmc_gt_rx_n
|
||||
create_bd_port -dir O fmc_gt_tx_p
|
||||
create_bd_port -dir O fmc_gt_tx_n
|
||||
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb/up_rstn
|
||||
ad_connect util_pzslb_gtlb/qpll_ref_clk fmc_gt_ref_clk0
|
||||
ad_connect util_pzslb_gtlb/cpll_ref_clk fmc_gt_ref_clk1
|
||||
ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb/gt_qpll_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb/gt_pll_0
|
||||
ad_connect util_pzslb_gtlb/rx_p fmc_gt_rx_p
|
||||
ad_connect util_pzslb_gtlb/rx_n fmc_gt_rx_n
|
||||
ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb/gt_rx_0
|
||||
ad_connect util_pzslb_gtlb/tx_p fmc_gt_tx_p
|
||||
ad_connect util_pzslb_gtlb/tx_n fmc_gt_tx_n
|
||||
ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb/rx_gt_comma_align_enb_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb/gt_tx_ip_0
|
||||
set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0]
|
||||
set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1]
|
||||
set util_pzslb_gtlb_2 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_2]
|
||||
set util_pzslb_gtlb_3 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_3]
|
||||
|
||||
ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
|
||||
|
||||
ad_cpu_interconnect 0x41200000 axi_gpio_0
|
||||
ad_cpu_interconnect 0x41210000 axi_gpio_1
|
||||
ad_cpu_interconnect 0x41220000 axi_gpio_2
|
||||
ad_cpu_interconnect 0x41230000 axi_gpio_3
|
||||
create_bd_port -dir I gt_ref_clk
|
||||
create_bd_port -dir I gt_rx_0_p
|
||||
create_bd_port -dir I gt_rx_0_n
|
||||
create_bd_port -dir O gt_tx_0_p
|
||||
create_bd_port -dir O gt_tx_0_n
|
||||
create_bd_port -dir I gt_rx_1_p
|
||||
create_bd_port -dir I gt_rx_1_n
|
||||
create_bd_port -dir O gt_tx_1_p
|
||||
create_bd_port -dir O gt_tx_1_n
|
||||
create_bd_port -dir I gt_rx_2_p
|
||||
create_bd_port -dir I gt_rx_2_n
|
||||
create_bd_port -dir O gt_tx_2_p
|
||||
create_bd_port -dir O gt_tx_2_n
|
||||
create_bd_port -dir I gt_rx_3_p
|
||||
create_bd_port -dir I gt_rx_3_n
|
||||
create_bd_port -dir O gt_tx_3_p
|
||||
create_bd_port -dir O gt_tx_3_n
|
||||
|
||||
create_bd_port -dir O up_clk
|
||||
create_bd_port -dir O up_rst
|
||||
create_bd_port -dir O up_rstn
|
||||
create_bd_port -dir I up_pn_err_clr
|
||||
create_bd_port -dir I up_pn_oos_clr
|
||||
create_bd_port -dir O up_pn_err
|
||||
create_bd_port -dir O up_pn_oos
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb_0/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
|
||||
ad_connect util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_0/rx_p gt_rx_0_p
|
||||
ad_connect util_pzslb_gtlb_0/rx_n gt_rx_0_n
|
||||
ad_connect util_pzslb_gtlb_0/tx_p gt_tx_0_p
|
||||
ad_connect util_pzslb_gtlb_0/tx_n gt_tx_0_n
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb_1/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
|
||||
ad_connect util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_1/rx_p gt_rx_1_p
|
||||
ad_connect util_pzslb_gtlb_1/rx_n gt_rx_1_n
|
||||
ad_connect util_pzslb_gtlb_1/tx_p gt_tx_1_p
|
||||
ad_connect util_pzslb_gtlb_1/tx_n gt_tx_1_n
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb_2/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb_2/up_rstn
|
||||
ad_connect util_pzslb_gtlb_2/qpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_2/cpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_2/rx_p gt_rx_2_p
|
||||
ad_connect util_pzslb_gtlb_2/rx_n gt_rx_2_n
|
||||
ad_connect util_pzslb_gtlb_2/tx_p gt_tx_2_p
|
||||
ad_connect util_pzslb_gtlb_2/tx_n gt_tx_2_n
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb_3/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb_3/up_rstn
|
||||
ad_connect util_pzslb_gtlb_3/qpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_3/cpll_ref_clk gt_ref_clk
|
||||
ad_connect util_pzslb_gtlb_3/rx_p gt_rx_3_p
|
||||
ad_connect util_pzslb_gtlb_3/rx_n gt_rx_3_n
|
||||
ad_connect util_pzslb_gtlb_3/tx_p gt_tx_3_p
|
||||
ad_connect util_pzslb_gtlb_3/tx_n gt_tx_3_n
|
||||
ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_2 util_pzslb_gtlb_2/gt_pll_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_2 util_pzslb_gtlb_2/gt_rx_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_2 util_pzslb_gtlb_2/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_2 util_pzslb_gtlb_2/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_2 util_pzslb_gtlb_2/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_2 util_pzslb_gtlb_2/rx_gt_comma_align_enb_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_3 util_pzslb_gtlb_3/gt_pll_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_3 util_pzslb_gtlb_3/gt_rx_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_3 util_pzslb_gtlb_3/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_3 util_pzslb_gtlb_3/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_3 util_pzslb_gtlb_3/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_3 util_pzslb_gtlb_3/rx_gt_comma_align_enb_0
|
||||
|
||||
ad_connect sys_cpu_clk up_clk
|
||||
ad_connect sys_cpu_reset up_rst
|
||||
ad_connect sys_cpu_resetn up_rstn
|
||||
ad_connect up_pn_err_clr util_pzslb_gtlb/up_pn_err_clr
|
||||
ad_connect up_pn_oos_clr util_pzslb_gtlb/up_pn_oos_clr
|
||||
ad_connect up_pn_err util_pzslb_gtlb/up_pn_err
|
||||
ad_connect up_pn_oos util_pzslb_gtlb/up_pn_oos
|
||||
# un-used io (regular)
|
||||
|
||||
set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
|
||||
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_0 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_1 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_2 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_5 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.NUM_OF_IO {7}] $axi_gpreg
|
||||
|
||||
ad_cpu_interconnect 0x41200000 axi_gpreg
|
||||
|
||||
ad_connect util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_0
|
||||
ad_connect util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_1
|
||||
ad_connect util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_2
|
||||
ad_connect util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_3
|
||||
ad_connect util_pzslb_gtlb_2/rx_clk axi_gpreg/d_clk_4
|
||||
ad_connect util_pzslb_gtlb_2/tx_clk axi_gpreg/d_clk_5
|
||||
ad_connect util_pzslb_gtlb_3/rx_clk axi_gpreg/d_clk_6
|
||||
ad_connect util_pzslb_gtlb_3/tx_clk axi_gpreg/d_clk_7
|
||||
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_0
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_1
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_2
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_0
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_1
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_2
|
||||
|
||||
ad_connect gp_in_0 axi_gpreg/up_gp_in_0
|
||||
ad_connect gp_in_1 axi_gpreg/up_gp_in_1
|
||||
ad_connect gp_in_2 axi_gpreg/up_gp_in_2
|
||||
ad_connect gp_out_0 axi_gpreg/up_gp_out_0
|
||||
ad_connect gp_out_1 axi_gpreg/up_gp_out_1
|
||||
ad_connect gp_out_2 axi_gpreg/up_gp_out_2
|
||||
ad_connect axi_gpreg/up_gp_in_3 util_pzslb_gtlb_0/up_gp_out
|
||||
ad_connect axi_gpreg/up_gp_out_3 util_pzslb_gtlb_0/up_gp_in
|
||||
ad_connect axi_gpreg/up_gp_in_4 util_pzslb_gtlb_1/up_gp_out
|
||||
ad_connect axi_gpreg/up_gp_out_4 util_pzslb_gtlb_1/up_gp_in
|
||||
ad_connect axi_gpreg/up_gp_in_5 util_pzslb_gtlb_2/up_gp_out
|
||||
ad_connect axi_gpreg/up_gp_out_5 util_pzslb_gtlb_2/up_gp_in
|
||||
ad_connect axi_gpreg/up_gp_in_6 util_pzslb_gtlb_3/up_gp_out
|
||||
ad_connect axi_gpreg/up_gp_out_6 util_pzslb_gtlb_3/up_gp_in
|
||||
|
||||
## temporary (remove ila indirectly)
|
||||
|
||||
delete_bd_objs [get_bd_cells ila_adc]
|
||||
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ ad_cpu_interconnect 0x77600000 axi_i2s_adi
|
|||
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
|
||||
|
||||
# usued io (gt)
|
||||
# un-used io (gt)
|
||||
|
||||
set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
|
||||
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pzslb_gt
|
||||
|
|
@ -229,7 +229,7 @@ ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
|
|||
ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0
|
||||
|
||||
# usued io (regular)
|
||||
# un-used io (regular)
|
||||
|
||||
set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
|
||||
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
|
||||
|
|
|
|||
Loading…
Reference in New Issue