From 1e074726dba06a6a048d4663a7e3ae2ca0e3dda5 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 14 Aug 2018 12:14:20 +0100 Subject: [PATCH] intel_serde: Rename alt_serdes to intel_serdes --- library/Makefile | 4 +- library/axi_ad9122/axi_ad9122_hw.tcl | 4 +- library/axi_ad9361/axi_ad9361_hw.tcl | 12 +- library/axi_ad9684/axi_ad9684_hw.tcl | 4 +- .../intel/common/alt_serdes/alt_serdes_hw.tcl | 132 ------------------ .../{alt_serdes => intel_serdes}/Makefile | 4 +- .../common/intel_serdes/intel_serdes_hw.tcl | 132 ++++++++++++++++++ 7 files changed, 146 insertions(+), 146 deletions(-) delete mode 100644 library/intel/common/alt_serdes/alt_serdes_hw.tcl rename library/intel/common/{alt_serdes => intel_serdes}/Makefile (81%) create mode 100644 library/intel/common/intel_serdes/intel_serdes_hw.tcl diff --git a/library/Makefile b/library/Makefile index 4acd11c56..976107c57 100644 --- a/library/Makefile +++ b/library/Makefile @@ -65,7 +65,7 @@ clean: $(MAKE) -C intel/avl_dacfifo clean $(MAKE) -C intel/axi_adxcvr clean $(MAKE) -C intel/common/alt_mem_asym clean - $(MAKE) -C intel/common/alt_serdes clean + $(MAKE) -C intel/common/intel_serdes clean $(MAKE) -C intel/jesd204_phy clean $(MAKE) -C intel/util_clkdiv clean $(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean @@ -175,7 +175,7 @@ lib: $(MAKE) -C intel/avl_dacfifo $(MAKE) -C intel/axi_adxcvr $(MAKE) -C intel/common/alt_mem_asym - $(MAKE) -C intel/common/alt_serdes + $(MAKE) -C intel/common/intel_serdes $(MAKE) -C intel/jesd204_phy $(MAKE) -C intel/util_clkdiv $(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc diff --git a/library/axi_ad9122/axi_ad9122_hw.tcl b/library/axi_ad9122/axi_ad9122_hw.tcl index f8c10af76..c621696bb 100644 --- a/library/axi_ad9122/axi_ad9122_hw.tcl +++ b/library/axi_ad9122/axi_ad9122_hw.tcl @@ -96,13 +96,13 @@ ad_alt_intf signal dac_dunf input 1 unf # SERDES instances and configurations -add_hdl_instance ad_serdes_clk_core_tx alt_serdes +add_hdl_instance ad_serdes_clk_core_tx intel_serdes set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK} set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1} set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8} set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0} -add_hdl_instance ad_serdes_out_core alt_serdes +add_hdl_instance ad_serdes_out_core intel_serdes set_instance_parameter_value ad_serdes_out_core {MODE} {OUT} set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1} set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8} diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index 1bf7cda02..f382987e6 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -175,22 +175,22 @@ proc axi_ad9361_elab {} { if {$m_fpga_technology eq "Arria 10"} { - add_hdl_instance axi_ad9361_serdes_clk alt_serdes - set_instance_parameter_value axi_ad9361_serdes_clk {FPGA_TECHNOLOGY} $m_fpga_technology + add_hdl_instance axi_ad9361_serdes_clk intel_serdes + set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} $m_fpga_technology set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK} set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0} - add_hdl_instance axi_ad9361_serdes_in alt_serdes - set_instance_parameter_value axi_ad9361_serdes_in {FPGA_TECHNOLOGY} $m_fpga_technology + add_hdl_instance axi_ad9361_serdes_in intel_serdes + set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} $m_fpga_technology set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN} set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0} - add_hdl_instance axi_ad9361_serdes_out alt_serdes - set_instance_parameter_value axi_ad9361_serdes_out {FPGA_TECHNOLOGY} $m_fpga_technology + add_hdl_instance axi_ad9361_serdes_out intel_serdes + set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} $m_fpga_technology set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT} set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4} diff --git a/library/axi_ad9684/axi_ad9684_hw.tcl b/library/axi_ad9684/axi_ad9684_hw.tcl index 46153fc33..7fd8ccf11 100644 --- a/library/axi_ad9684/axi_ad9684_hw.tcl +++ b/library/axi_ad9684/axi_ad9684_hw.tcl @@ -96,13 +96,13 @@ ad_alt_intf signal adc_dovf input 1 ovf # SERDES instances and configurations -add_hdl_instance ad_serdes_clk_core_rx alt_serdes +add_hdl_instance ad_serdes_clk_core_rx intel_serdes set_instance_parameter_value ad_serdes_clk_core_rx {MODE} {CLK} set_instance_parameter_value ad_serdes_clk_core_rx {DDR_OR_SDR_N} {1} set_instance_parameter_value ad_serdes_clk_core_rx {SERDES_FACTOR} {4} set_instance_parameter_value ad_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0} -add_hdl_instance ad_serdes_in_core alt_serdes +add_hdl_instance ad_serdes_in_core intel_serdes set_instance_parameter_value ad_serdes_in_core {MODE} {IN} set_instance_parameter_value ad_serdes_in_core {DDR_OR_SDR_N} {1} set_instance_parameter_value ad_serdes_in_core {SERDES_FACTOR} {4} diff --git a/library/intel/common/alt_serdes/alt_serdes_hw.tcl b/library/intel/common/alt_serdes/alt_serdes_hw.tcl deleted file mode 100644 index 4f03f4eb4..000000000 --- a/library/intel/common/alt_serdes/alt_serdes_hw.tcl +++ /dev/null @@ -1,132 +0,0 @@ - -package require qsys - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl - -ad_ip_create alt_serdes {Altera SERDES} -set_module_property COMPOSITION_CALLBACK p_alt_serdes - -# parameters - -ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} -ad_ip_parameter MODE STRING "CLK" false -ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false -ad_ip_parameter SERDES_FACTOR INTEGER 8 false -ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false - -set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"} -set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1} -set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8} -set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz" - -proc p_alt_serdes {} { - - set m_mode [get_parameter_value "MODE"] - set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"] - set m_serdes_factor [get_parameter_value "SERDES_FACTOR"] - set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"] - - set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))] - set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)] - - set m_ls_phase 22.5 - set m_ld_phase 315.0 - set m_ld_duty_cycle 12.5 - - if {$m_serdes_factor == 4} { - set m_ls_phase 45 - set m_ld_phase 270.0 - set m_ld_duty_cycle 25.0 - } - - ## arria 10 only - - if {$m_mode == "CLK"} { - add_instance alt_serdes_pll altera_iopll - set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency - set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} - set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} - set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3} - set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0} - set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true} - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase - set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase - set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} - add_interface rst reset sink - set_interface_property rst EXPORT_OF alt_serdes_pll.reset - add_interface ref_clk clock sink - set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk - add_interface locked conduit end - set_interface_property locked EXPORT_OF alt_serdes_pll.locked - add_interface hs_phase conduit end - set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout - add_interface hs_clk conduit end - set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk - add_interface loaden conduit end - set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden - add_interface ls_clk clock source - set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 - return - } - - if {$m_mode == "IN"} { - add_instance alt_serdes_in altera_lvds - set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO} - set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1} - set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate - set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor - set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true} - set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency - set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false} - add_interface data_in conduit end - set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in - add_interface clk conduit end - set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk - add_interface loaden conduit end - set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden - add_interface div_clk conduit end - set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock - add_interface hs_phase conduit end - set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph - add_interface locked conduit end - set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked - add_interface data_s conduit end - set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out - add_interface delay_locked conduit end - set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked - return - } - - if {$m_mode == "OUT"} { - add_instance alt_serdes_out altera_lvds - set_instance_parameter_value alt_serdes_out {MODE} {TX} - set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1} - set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate - set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor - set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false} - set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false} - set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true} - set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency - set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false} - add_interface data_out conduit end - set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out - add_interface clk conduit end - set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk - add_interface loaden conduit end - set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden - add_interface div_clk conduit end - set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock - add_interface data_s conduit end - set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in - return - } -} - diff --git a/library/intel/common/alt_serdes/Makefile b/library/intel/common/intel_serdes/Makefile similarity index 81% rename from library/intel/common/alt_serdes/Makefile rename to library/intel/common/intel_serdes/Makefile index 8d223a089..26ea26c32 100644 --- a/library/intel/common/alt_serdes/Makefile +++ b/library/intel/common/intel_serdes/Makefile @@ -3,8 +3,8 @@ ## Auto-generated, do not modify! #################################################################################### -LIBRARY_NAME := alt_serdes +LIBRARY_NAME := intel_serdes -INTEL_DEPS += alt_serdes_hw.tcl +INTEL_DEPS += intel_serdes_hw.tcl include ../../../scripts/library.mk diff --git a/library/intel/common/intel_serdes/intel_serdes_hw.tcl b/library/intel/common/intel_serdes/intel_serdes_hw.tcl new file mode 100644 index 000000000..34f621196 --- /dev/null +++ b/library/intel/common/intel_serdes/intel_serdes_hw.tcl @@ -0,0 +1,132 @@ + +package require qsys + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create intel_serdes {Intel SERDES} +set_module_property COMPOSITION_CALLBACK p_intel_serdes + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter MODE STRING "CLK" false +ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false +ad_ip_parameter SERDES_FACTOR INTEGER 8 false +ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false + +set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"} +set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1} +set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8} +set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz" + +proc p_intel_serdes {} { + + set m_mode [get_parameter_value "MODE"] + set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"] + set m_serdes_factor [get_parameter_value "SERDES_FACTOR"] + set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"] + + set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))] + set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)] + + set m_ls_phase 22.5 + set m_ld_phase 315.0 + set m_ld_duty_cycle 12.5 + + if {$m_serdes_factor == 4} { + set m_ls_phase 45 + set m_ld_phase 270.0 + set m_ld_duty_cycle 25.0 + } + + ## arria 10 only + + if {$m_mode == "CLK"} { + add_instance intel_serdes_pll altera_iopll + set_instance_parameter_value intel_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency + set_instance_parameter_value intel_serdes_pll {gui_use_locked} {1} + set_instance_parameter_value intel_serdes_pll {gui_operation_mode} {lvds} + set_instance_parameter_value intel_serdes_pll {gui_number_of_clocks} {3} + set_instance_parameter_value intel_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0} + set_instance_parameter_value intel_serdes_pll {gui_en_phout_ports} {true} + set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate + set_instance_parameter_value intel_serdes_pll {gui_ps_units0} {degrees} + set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg0} {180.0} + set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate + set_instance_parameter_value intel_serdes_pll {gui_ps_units1} {degrees} + set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg1} $m_ld_phase + set_instance_parameter_value intel_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle + set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate + set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg2} $m_ls_phase + set_instance_parameter_value intel_serdes_pll {gui_ps_units2} {degrees} + add_interface rst reset sink + set_interface_property rst EXPORT_OF intel_serdes_pll.reset + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF intel_serdes_pll.refclk + add_interface locked conduit end + set_interface_property locked EXPORT_OF intel_serdes_pll.locked + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF intel_serdes_pll.phout + add_interface hs_clk conduit end + set_interface_property hs_clk EXPORT_OF intel_serdes_pll.lvds_clk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF intel_serdes_pll.loaden + add_interface ls_clk clock source + set_interface_property ls_clk EXPORT_OF intel_serdes_pll.outclk2 + return + } + + if {$m_mode == "IN"} { + add_instance intel_serdes_in altera_lvds + set_instance_parameter_value intel_serdes_in {MODE} {RX_DPA-FIFO} + set_instance_parameter_value intel_serdes_in {NUM_CHANNELS} {1} + set_instance_parameter_value intel_serdes_in {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value intel_serdes_in {J_FACTOR} $m_serdes_factor + set_instance_parameter_value intel_serdes_in {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value intel_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value intel_serdes_in {PLL_USE_RESET} {false} + add_interface data_in conduit end + set_interface_property data_in EXPORT_OF intel_serdes_in.rx_in + add_interface clk conduit end + set_interface_property clk EXPORT_OF intel_serdes_in.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF intel_serdes_in.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF intel_serdes_in.ext_coreclock + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF intel_serdes_in.ext_vcoph + add_interface locked conduit end + set_interface_property locked EXPORT_OF intel_serdes_in.ext_pll_locked + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF intel_serdes_in.rx_out + add_interface delay_locked conduit end + set_interface_property delay_locked EXPORT_OF intel_serdes_in.rx_dpa_locked + return + } + + if {$m_mode == "OUT"} { + add_instance intel_serdes_out altera_lvds + set_instance_parameter_value intel_serdes_out {MODE} {TX} + set_instance_parameter_value intel_serdes_out {NUM_CHANNELS} {1} + set_instance_parameter_value intel_serdes_out {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value intel_serdes_out {J_FACTOR} $m_serdes_factor + set_instance_parameter_value intel_serdes_out {TX_EXPORT_CORECLOCK} {false} + set_instance_parameter_value intel_serdes_out {TX_USE_OUTCLOCK} {false} + set_instance_parameter_value intel_serdes_out {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value intel_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value intel_serdes_out {PLL_USE_RESET} {false} + add_interface data_out conduit end + set_interface_property data_out EXPORT_OF intel_serdes_out.tx_out + add_interface clk conduit end + set_interface_property clk EXPORT_OF intel_serdes_out.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF intel_serdes_out.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF intel_serdes_out.ext_coreclock + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF intel_serdes_out.tx_in + return + } +} +