axi_ad9361- add receive init delay
parent
b0e88eb5ff
commit
1ef064ac03
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@ -46,11 +46,13 @@ module axi_ad9361 #(
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parameter DEVICE_TYPE = 0,
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parameter TDD_DISABLE = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter ADC_INIT_DELAY = 0,
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parameter ADC_DATAPATH_DISABLE = 0,
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parameter ADC_USERPORTS_DISABLE = 0,
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parameter ADC_DATAFORMAT_DISABLE = 0,
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parameter ADC_DCFILTER_DISABLE = 0,
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parameter ADC_IQCORRECTION_DISABLE = 0,
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parameter DAC_INIT_DELAY = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter DAC_DDS_DISABLE = 0,
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@ -527,6 +529,7 @@ module axi_ad9361 #(
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axi_ad9361_rx #(
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.ID (ID),
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.MODE_1R1T (MODE_1R1T),
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.INIT_DELAY (ADC_INIT_DELAY),
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.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
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.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
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.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
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@ -586,6 +589,7 @@ module axi_ad9361 #(
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axi_ad9361_tx #(
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.ID (ID),
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.MODE_1R1T (MODE_1R1T),
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.INIT_DELAY (DAC_INIT_DELAY),
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.DDS_DISABLE (DAC_DDS_DISABLE_INT),
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.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
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.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
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@ -44,6 +44,7 @@ module axi_ad9361_rx #(
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter INIT_DELAY = 0,
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parameter USERPORTS_DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0,
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parameter DCFILTER_DISABLE = 0,
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@ -370,6 +371,7 @@ module axi_ad9361_rx #(
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// adc delay control
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up_delay_cntrl #(
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.INIT_DELAY (INIT_DELAY),
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.DATA_WIDTH (13),
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.BASE_ADDRESS (6'h02))
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i_delay_cntrl (
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@ -43,6 +43,7 @@ module axi_ad9361_tx #(
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter INIT_DELAY = 0,
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parameter DDS_DISABLE = 0,
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parameter USERPORTS_DISABLE = 0,
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parameter DELAYCNTRL_DISABLE = 0,
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@ -371,6 +372,7 @@ module axi_ad9361_tx #(
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up_delay_cntrl #(
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.DISABLE (DELAYCNTRL_DISABLE),
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.INIT_DELAY (INIT_DELAY),
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.DATA_WIDTH(16),
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.BASE_ADDRESS(6'h12))
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i_delay_cntrl (
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