axi_ad9361- add receive init delay

main
Rejeesh Kutty 2017-03-13 16:28:38 -04:00
parent b0e88eb5ff
commit 1ef064ac03
3 changed files with 8 additions and 0 deletions

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@ -46,11 +46,13 @@ module axi_ad9361 #(
parameter DEVICE_TYPE = 0,
parameter TDD_DISABLE = 0,
parameter CMOS_OR_LVDS_N = 0,
parameter ADC_INIT_DELAY = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter ADC_USERPORTS_DISABLE = 0,
parameter ADC_DATAFORMAT_DISABLE = 0,
parameter ADC_DCFILTER_DISABLE = 0,
parameter ADC_IQCORRECTION_DISABLE = 0,
parameter DAC_INIT_DELAY = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter DAC_DATAPATH_DISABLE = 0,
parameter DAC_DDS_DISABLE = 0,
@ -527,6 +529,7 @@ module axi_ad9361 #(
axi_ad9361_rx #(
.ID (ID),
.MODE_1R1T (MODE_1R1T),
.INIT_DELAY (ADC_INIT_DELAY),
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
@ -586,6 +589,7 @@ module axi_ad9361 #(
axi_ad9361_tx #(
.ID (ID),
.MODE_1R1T (MODE_1R1T),
.INIT_DELAY (DAC_INIT_DELAY),
.DDS_DISABLE (DAC_DDS_DISABLE_INT),
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),

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@ -44,6 +44,7 @@ module axi_ad9361_rx #(
parameter ID = 0,
parameter MODE_1R1T = 0,
parameter INIT_DELAY = 0,
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
@ -370,6 +371,7 @@ module axi_ad9361_rx #(
// adc delay control
up_delay_cntrl #(
.INIT_DELAY (INIT_DELAY),
.DATA_WIDTH (13),
.BASE_ADDRESS (6'h02))
i_delay_cntrl (

View File

@ -43,6 +43,7 @@ module axi_ad9361_tx #(
parameter ID = 0,
parameter MODE_1R1T = 0,
parameter INIT_DELAY = 0,
parameter DDS_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter DELAYCNTRL_DISABLE = 0,
@ -371,6 +372,7 @@ module axi_ad9361_tx #(
up_delay_cntrl #(
.DISABLE (DELAYCNTRL_DISABLE),
.INIT_DELAY (INIT_DELAY),
.DATA_WIDTH(16),
.BASE_ADDRESS(6'h12))
i_delay_cntrl (