From 1ef83bd88b41b0001ca7e51704ff85bcfaeb9cbc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Sat, 23 May 2015 00:16:27 +0300
Subject: [PATCH] axi_ad9671: Updated port names. Fixed synchronization of the
 rx_sof with the ad_jesd_align module, so that data valid is assigned
 correctly

---
 library/axi_ad9671/axi_ad9671.v    |  6 +++---
 library/axi_ad9671/axi_ad9671_if.v | 11 ++++++-----
 library/common/ad_jesd_align.v     |  5 +++--
 3 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v
index 4e2ce1f9b..27f4fbcb9 100644
--- a/library/axi_ad9671/axi_ad9671.v
+++ b/library/axi_ad9671/axi_ad9671.v
@@ -46,7 +46,7 @@ module axi_ad9671 (
 
   rx_clk,
   rx_data,
-  rx_data_sof,
+  rx_sof,
 
   // dma interface
 
@@ -95,7 +95,7 @@ module axi_ad9671 (
 
   input                                 rx_clk;
   input   [(64*PCORE_4L_2L_N)+63:0]     rx_data;
-  input                                 rx_data_sof;
+  input                                 rx_sof;
 
   // dma interface
 
@@ -206,7 +206,7 @@ module axi_ad9671 (
   ) i_if (
     .rx_clk (rx_clk),
     .rx_data (rx_data),
-    .rx_data_sof (rx_data_sof),
+    .rx_sof (rx_sof),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid_s),
diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v
index 51061132f..89bab9e39 100644
--- a/library/axi_ad9671/axi_ad9671_if.v
+++ b/library/axi_ad9671/axi_ad9671_if.v
@@ -36,7 +36,6 @@
 // ***************************************************************************
 // ***************************************************************************
 // ***************************************************************************
-// This is the LVDS/DDR interface
 
 `timescale 1ns/100ps
 
@@ -46,7 +45,7 @@ module axi_ad9671_if (
   // rx_clk is (line-rate/40)
 
   rx_clk,
-  rx_data_sof,
+  rx_sof,
   rx_data,
 
   // adc data output
@@ -88,7 +87,7 @@ module axi_ad9671_if (
   // rx_clk is (line-rate/40)
 
   input                                 rx_clk;
-  input                                 rx_data_sof;
+  input                                 rx_sof;
   input   [(64*PCORE_4L_2L_N)+63:0]     rx_data;
 
   // adc data output
@@ -142,6 +141,7 @@ module axi_ad9671_if (
   reg     [127:0]                       int_data = 'd0;
   reg                                   adc_status = 'd0;
   reg                                   adc_sync_status = 'd0;
+  reg                                   rx_sof_d = 'd0;
 
   reg     [  3:0]                       adc_waddr = 'd0;
   reg     [  3:0]                       adc_raddr_out = 'd0;
@@ -219,9 +219,10 @@ module axi_ad9671_if (
   always @(posedge rx_clk) begin
     if (PCORE_4L_2L_N == 1'b1) begin
       int_valid <= 1'b1;
-      int_data <= rx_data;
+      int_data  <= rx_data;
     end else begin
-      int_valid         <= !rx_data_sof;
+      rx_sof_d          <= rx_sof;
+      int_valid         <= rx_sof_d;
       int_data[63:0]    <= {rx_data[31:0], int_data[63:32]};
       int_data[127:64]  <= {rx_data[63:32], int_data[127:96]};
     end
diff --git a/library/common/ad_jesd_align.v b/library/common/ad_jesd_align.v
index cb03e22db..d70ffa2e3 100644
--- a/library/common/ad_jesd_align.v
+++ b/library/common/ad_jesd_align.v
@@ -63,16 +63,17 @@ module ad_jesd_align (
   reg     [31:0]  rx_ip_data_d = 'd0;
   reg     [ 3:0]  rx_ip_sof_hold = 'd0;
   reg             rx_sof = 'd0;
+  reg             rx_ip_sof_d = 'd0;
   reg     [31:0]  rx_data = 'd0;
 
   // dword may contain more than one frame per clock
-
   always @(posedge rx_clk) begin
     rx_ip_data_d <= rx_ip_data;
+    rx_ip_sof_d <= rx_ip_sof;
     if (rx_ip_sof != 4'h0) begin
       rx_ip_sof_hold <= rx_ip_sof;
     end
-    rx_sof <= |rx_ip_sof;
+    rx_sof <= |rx_ip_sof_d;
     if (rx_ip_sof_hold[0] == 1'b1) begin
       rx_data <= rx_ip_data;
     end else if (rx_ip_sof_hold[1] == 1'b1) begin