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axi_dacfifo: Redesign the bypass functionality

main
Istvan Csomortani 2017-02-23 17:32:31 +02:00
parent 573959c826
commit 1fce57f6c3
7 changed files with 390 additions and 46 deletions
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1
library/xilinx/axi_dacfifo/Makefile
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@ -16,6 +16,7 @@ M_DEPS += axi_dacfifo_dac.v
M_DEPS += axi_dacfifo_ip.tcl
M_DEPS += axi_dacfifo_rd.v
M_DEPS += axi_dacfifo_wr.v
M_DEPS += axi_dacfifo_bypass.v
M_VIVADO := vivado -mode batch -source

89
library/xilinx/axi_dacfifo/axi_dacfifo.v
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@ -59,7 +59,7 @@ module axi_dacfifo (
dac_dunf,
dac_xfer_out,
dac_fifo_bypass,
bypass,
// axi interface
@ -136,7 +136,7 @@ module axi_dacfifo (
output dac_dunf;
output dac_xfer_out;
input dac_fifo_bypass;
input bypass;
// axi interface
@ -185,6 +185,17 @@ module axi_dacfifo (
input [(AXI_DATA_WIDTH-1):0] axi_rdata;
output axi_rready;
reg dma_ready = 1'b0;
reg dma_bypass_m1 = 1'b0;
reg dma_bypass = 1'b0;
reg dac_bypass_m1 = 1'b0;
reg dac_bypass = 1'b0;
reg dac_xfer_out = 1'b0;
reg dac_xfer_out_m1 = 1'b0;
reg dac_xfer_out_bypass = 1'b0;
reg dac_dunf = 1'b0;
reg [(DAC_DATA_WIDTH-1):0] dac_data = 'b0;
// internal signals
wire [(AXI_DATA_WIDTH-1):0] axi_wr_data_s;
@ -206,6 +217,12 @@ module axi_dacfifo (
wire dma_valid_bp_s;
wire [(AXI_DATA_WIDTH-1):0] dma_data_bp_s;
wire dma_ready_bp_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;
wire dac_xfer_fifo_out_s;
wire dac_dunf_fifo_s;
wire dac_dunf_bypass_s;
wire dma_ready_wr_s;
axi_dacfifo_wr #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@ -217,7 +234,8 @@ module axi_dacfifo (
) i_wr (
.dma_clk (dma_clk),
.dma_data (dma_data),
.dma_ready (dma_ready_s),
.dma_ready (dma_ready),
.dma_ready_out (dma_ready_wr_s),
.dma_valid (dma_valid),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_last (dma_xfer_last),
@ -294,8 +312,8 @@ module axi_dacfifo (
.DAC_DATA_WIDTH (DAC_DATA_WIDTH)
) i_dac (
.axi_clk (axi_clk),
.axi_dvalid (dac_rd_valid_s),
.axi_ddata (dac_rd_data_s),
.axi_dvalid (dac_valid),
.axi_ddata (axi_rd_data_s),
.axi_dready (axi_rd_ready_s),
.axi_dlast (axi_dlast_s),
.axi_xfer_req (axi_xfer_req_s),
@ -303,29 +321,54 @@ module axi_dacfifo (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_data (dac_data),
.dac_xfer_out (dac_xfer_out),
.dac_dunf (dac_dunf));
.dac_data (dac_data_fifo_s),
.dac_xfer_out (dac_xfer_fifo_out_s),
.dac_dunf (dac_dunf_fifo_s));
// bypass logic
util_axis_resize #(
.MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
.SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
) i_util_axis_resize (
.clk (axi_clk),
.resetn (axi_resetn),
.s_valid (dma_valid),
.s_ready (dma_ready_bp_s),
.s_data (dma_data),
.m_valid (dma_valid_bp_s),
.m_ready (axi_rd_ready_s),
.m_data (dma_data_bp_s)
axi_dacfifo_bypass #(
.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH)
) i_dacfifo_bypass (
.dma_clk(dma_clk),
.dma_data(dma_data),
.dma_ready(dma_ready),
.dma_ready_out(dma_ready_bypass_s),
.dma_valid(dma_valid),
.dma_xfer_req(dma_xfer_req),
.dac_clk(dac_clk),
.dac_rst(dac_rst),
.dac_valid(dac_valid),
.dac_data(dac_data_bypass_s),
.dac_dunf(dac_dunf_bypass_s)
);
assign dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
assign dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
assign dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
always @(posedge dma_clk) begin
dma_bypass_m1 <= bypass;
dma_bypass <= dma_bypass_m1;
end
always @(posedge dac_clk) begin
dac_bypass_m1 <= bypass;
dac_bypass <= dac_bypass_m1;
dac_xfer_out_m1 <= dma_xfer_req;
dac_xfer_out_bypass <= dac_xfer_out_m1;
end
// mux for the dma_ready
always @(posedge dma_clk) begin
dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s;
end
// mux for dac data
always @(posedge dac_clk) begin
dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
end
endmodule

292
library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v Normal file
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@ -0,0 +1,292 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2016(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dacfifo_bypass #(
parameter DAC_DATA_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64) (
// dma fifo interface
input dma_clk,
input [(DMA_DATA_WIDTH-1):0] dma_data,
input dma_ready,
output reg dma_ready_out,
input dma_valid,
// request and syncronizaiton
input dma_xfer_req,
// dac fifo interface
input dac_clk,
input dac_rst,
input dac_valid,
output reg [(DAC_DATA_WIDTH-1):0] dac_data,
output reg dac_dunf
);
// suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
DAC_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DAC_ADDRESS_WIDTH = 10;
localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
(MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) :
(MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) :
((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3));
localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;
localparam DAC_BUF_THRESHOLD_LO = 4;
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
reg dma_rst_m1 = 1'b0;
reg dma_rst = 1'b0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 1'b0;
reg [DAC_ADDRESS_WIDTH-1:0] dac_mem_addr_diff = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 1'b0;
reg dac_mem_ready = 1'b0;
reg dac_xfer_out = 1'b0;
reg dac_xfer_out_m1 = 1'b0;
// internal signals
wire dma_mem_last_read_s;
wire [(DMA_ADDRESS_WIDTH):0] dma_mem_addr_diff_s;
wire [(DAC_ADDRESS_WIDTH):0] dac_mem_addr_diff_s;
wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s;
wire dma_mem_wea_s;
wire dac_mem_rea_s;
wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s;
wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s;
wire [DAC_ADDRESS_WIDTH:0] dac_address_diff_s;
// binary to grey conversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// An asymmetric memory to transfer data from DMAC interface to DAC interface
ad_mem_asym #(
.A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
.A_DATA_WIDTH (DMA_DATA_WIDTH),
.B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH),
.B_DATA_WIDTH (DAC_DATA_WIDTH))
i_mem_asym (
.clka (dma_clk),
.wea (dma_mem_wea_s),
.addra (dma_mem_waddr),
.dina (dma_data),
.clkb (dac_clk),
.addrb (dac_mem_raddr),
.doutb (dac_mem_rdata_s));
// dma reset is brought from dac domain
always @(posedge dma_clk) begin
dma_rst_m1 <= dac_rst;
dma_rst <= dma_rst_m1;
end
// Write address generation for the asymmetric memory
assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_mem_waddr <= 'h0;
dma_mem_waddr_g <= 'h0;
end else begin
if (dma_mem_wea_s == 1'b1) begin
dma_mem_waddr <= dma_mem_waddr + 1;
end
dma_mem_waddr_g <= b2g(dma_mem_waddr);
end
end
// The memory module request data until reaches the high threshold.
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_mem_addr_diff <= 'b0;
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;
dma_mem_raddr <= 'b0;
dma_ready_out <= 1'b0;
end else begin
dma_mem_raddr_m1 <= dac_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
dma_mem_raddr <= g2b(dma_mem_raddr_m2);
dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
dma_ready_out <= 1'b0;
end else begin
dma_ready_out <= 1'b1;
end
end
end
// relative address offset on dma domain
assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dma_mem_raddr) :
(MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) :
(MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) :
((MEM_RATIO == 1) ? (dma_mem_raddr) :
(MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
(MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
// relative address offset on dac domain
assign dac_address_diff_s = {1'b1, dac_mem_raddr} - dac_mem_waddr_s;
assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dac_mem_waddr) :
(MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) :
(MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) :
((MEM_RATIO == 1) ? (dac_mem_waddr) :
(MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) :
(MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0}));
// Read address generation for the asymmetric memory
assign dac_mem_rea_s = dac_valid & dac_mem_ready;
always @(posedge dma_clk) begin
if (dac_rst == 1'b1) begin
dac_mem_raddr <= 'h0;
dac_mem_raddr_g <= 'h0;
end else begin
if (dac_mem_rea_s == 1'b1) begin
dac_mem_raddr <= dac_mem_raddr + 1;
end
dac_mem_raddr_g <= b2g(dac_mem_raddr);
end
end
// The memory module is ready if it's not empty
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_mem_addr_diff <= 'b0;
dac_mem_waddr_m1 <= 'b0;
dac_mem_waddr_m2 <= 'b0;
dac_mem_waddr <= 'b0;
dac_mem_ready <= 1'b0;
end else begin
dac_mem_waddr_m1 <= dma_mem_waddr_g;
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
dac_mem_waddr <= g2b(dac_mem_waddr_m2);
dac_mem_addr_diff <= dac_address_diff_s[DAC_ADDRESS_WIDTH-1:0];
if (dac_mem_addr_diff > 0) begin
dac_mem_ready <= 1'b1;
end else begin
dac_mem_ready <= 1'b0;
end
end
end
// define underflow
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_xfer_out_m1 <= 1'b0;
dac_xfer_out <= 1'b0;
dac_dunf <= 1'b0;
end else begin
dac_xfer_out_m1 <= dma_xfer_req;
dac_xfer_out <= dac_xfer_out_m1;
dac_dunf <= (dac_valid == 1'b1) ? (dac_xfer_out & ~dac_mem_ready) : dac_dunf;
end
end
// DAC data output logic
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_data <= 0;
end else begin
dac_data <= dac_mem_rdata_s;
end
end
endmodule

39
library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
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@ -1,24 +1,29 @@
set_property ASYNC_REG TRUE \
[get_cells -hier *_xfer_req_m[0]*] \
[get_cells -hier *_xfer_last_m[0]*]
[get_cells -hier *_xfer_req_m*] \
[get_cells -hier *_xfer_last_m*] \
[get_cells -hier *dac_xfer_out*] \
[get_cells -hier *dac_bypass_*] \
[get_cells -hier *dma_bypass_*]
set_false_path -to [get_cells *_xfer_req_m[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -to [get_cells *_xfer_last_m[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -to [get_cells *dma_rst_m1* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_last_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dma_rst_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]

1
library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
View File

@ -13,6 +13,7 @@ adi_ip_files axi_dacfifo [list \
"axi_dacfifo_dac.v" \
"axi_dacfifo_wr.v" \
"axi_dacfifo_rd.v" \
"axi_dacfifo_bypass.v" \
"axi_dacfifo.v"]
adi_ip_properties_lite axi_dacfifo

12
library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
View File

@ -46,6 +46,7 @@ module axi_dacfifo_wr (
dma_clk,
dma_data,
dma_ready,
dma_ready_out,
dma_valid,
// request and syncronizaiton
@ -120,7 +121,8 @@ module axi_dacfifo_wr (
input dma_clk;
input [(DMA_DATA_WIDTH-1):0] dma_data;
output dma_ready;
input dma_ready;
output dma_ready_out;
input dma_valid;
input dma_xfer_req;
@ -169,7 +171,7 @@ module axi_dacfifo_wr (
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0;
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;
reg dma_ready = 1'b0;
reg dma_ready_out = 1'b0;
reg dma_rst_m1 = 1'b0;
reg dma_rst_m2 = 1'b0;
reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0;
@ -363,16 +365,16 @@ module axi_dacfifo_wr (
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;
dma_mem_raddr <= 'b0;
dma_ready <= 1'b0;
dma_ready_out <= 1'b0;
end else begin
dma_mem_raddr_m1 <= axi_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
dma_mem_raddr <= g2b(dma_mem_raddr_m2);
dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
dma_ready <= 1'b0;
dma_ready_out <= 1'b0;
end else begin
dma_ready <= 1'b1;
dma_ready_out <= 1'b1;
end
end
end

2
projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
View File

@ -79,7 +79,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
ad_connect dma_xfer_req axi_dacfifo/dma_xfer_req
ad_connect dma_xfer_last axi_dacfifo/dma_xfer_last
ad_connect dac_fifo_bypass axi_dacfifo/dac_fifo_bypass
ad_connect dac_fifo_bypass axi_dacfifo/bypass
ad_connect dac_valid axi_dacfifo/dac_valid
ad_connect dac_data axi_dacfifo/dac_data
ad_connect dac_dunf axi_dacfifo/dac_dunf