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fmcadc2: Update common design to Vivado 2016.2

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AndreiGrozav 2016-08-30 16:42:58 +03:00
parent 6f0d124861
commit 2015bcedaa
1 changed files with 1 additions and 1 deletions
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projects/fmcadc2/common/fmcadc2_bd.tcl
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@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd