projects/common: Cosmetic changes.

main
Istvan Csomortani 2015-08-25 09:58:32 +03:00
parent f08305c979
commit 203d7cb470
8 changed files with 35 additions and 35 deletions

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@ -40,8 +40,8 @@ set_property -dict [list CONFIG.DMA_TYPE {0}] $axi_spdif_tx_core
set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_spdif_tx_dma
set_property -dict [list CONFIG.C_SG_INCLUDE_STSCNTRL_STRM {0}] $axi_spdif_tx_dma
# hdmi

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@ -107,9 +107,9 @@ set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.2 a
set_property -dict [list CONFIG.PHY_TYPE {RGMII}] $axi_ethernet
set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
set_property -dict [list CONFIG.C_INCLUDE_MM2S_DRE {1}] $axi_ethernet_dma
set_property -dict [list CONFIG.C_SG_USE_STSAPP_LENGTH {1}] $axi_ethernet_dma
set_property -dict [list CONFIG.C_INCLUDE_S2MM_DRE {1}] $axi_ethernet_dma
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]

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@ -163,7 +163,7 @@ ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB
ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG
ad_connect axi_intc/interrupt sys_mb/INTERRUPT
ad_connect axi_intc/intr sys_concat_intc/dout
ad_connect axi_intc/intr sys_concat_intc/dout
# defaults (peripherals)
@ -181,7 +181,7 @@ ad_connect sys_cpu_clk sys_dlmb/LMB_Clk
ad_connect sys_cpu_clk sys_ilmb/LMB_Clk
ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk
ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk
ad_connect sys_cpu_clk axi_ethernet/axis_clk
ad_connect sys_cpu_clk axi_ethernet/axis_clk
# defaults (interrupts)
@ -223,7 +223,7 @@ ad_connect axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL
ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
ad_connect phy_sd axi_ethernet/signal_detect
ad_connect sys_cpu_resetn phy_rst_n
ad_connect sys_cpu_resetn phy_rst_n
ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet/clk125m
ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet_rstgen/slowest_sync_clk
ad_connect axi_ethernet_clkgen/clk_out2 axi_ethernet/clk312
@ -247,13 +247,13 @@ ad_connect spi_clk_o axi_spi/sck_o
ad_connect spi_sdo_i axi_spi/io0_i
ad_connect spi_sdo_o axi_spi/io0_o
ad_connect spi_sdi_i axi_spi/io1_i
ad_connect gpio0_i axi_gpio/gpio_io_i
ad_connect gpio0_o axi_gpio/gpio_io_o
ad_connect gpio0_t axi_gpio/gpio_io_t
ad_connect gpio1_i axi_gpio/gpio2_io_i
ad_connect gpio1_o axi_gpio/gpio2_io_o
ad_connect gpio1_t axi_gpio/gpio2_io_t
ad_connect sys_cpu_clk axi_spi/ext_spi_clk
ad_connect gpio0_i axi_gpio/gpio_io_i
ad_connect gpio0_o axi_gpio/gpio_io_o
ad_connect gpio0_t axi_gpio/gpio_io_t
ad_connect gpio1_i axi_gpio/gpio2_io_i
ad_connect gpio1_o axi_gpio/gpio2_io_o
ad_connect gpio1_t axi_gpio/gpio2_io_t
ad_connect sys_cpu_clk axi_spi/ext_spi_clk
# defaults (interconnect - processor)

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@ -105,9 +105,9 @@ set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
@ -204,7 +204,7 @@ ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
ad_connect i2s axi_i2s_adi/I2S

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@ -234,7 +234,7 @@ ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
ad_connect spdif axi_spdif_tx_core/spdif_tx_o

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@ -173,7 +173,7 @@ ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
ad_connect spdif axi_spdif_tx_core/spdif_tx_o

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@ -97,9 +97,9 @@ set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
@ -176,7 +176,7 @@ ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
ad_connect spdif axi_spdif_tx_core/spdif_tx_o

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@ -119,9 +119,9 @@ set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
@ -154,13 +154,13 @@ ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
# interface connections
ad_connect ddr sys_ps7/DDR
ad_connect gpio_i sys_ps7/GPIO_I
ad_connect gpio_o sys_ps7/GPIO_O
ad_connect gpio_t sys_ps7/GPIO_T
ad_connect fixed_io sys_ps7/FIXED_IO
ad_connect iic_fmc axi_iic_fmc/iic
ad_connect sys_200m_clk axi_hdmi_clkgen/clk
ad_connect ddr sys_ps7/DDR
ad_connect gpio_i sys_ps7/GPIO_I
ad_connect gpio_o sys_ps7/GPIO_O
ad_connect gpio_t sys_ps7/GPIO_T
ad_connect fixed_io sys_ps7/FIXED_IO
ad_connect iic_fmc axi_iic_fmc/iic
ad_connect sys_200m_clk axi_hdmi_clkgen/clk
ad_connect axi_iic_main/IIC sys_i2c_mixer/upstream