projects/common: Cosmetic changes.
parent
f08305c979
commit
203d7cb470
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@ -40,8 +40,8 @@ set_property -dict [list CONFIG.DMA_TYPE {0}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
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set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.C_SG_INCLUDE_STSCNTRL_STRM {0}] $axi_spdif_tx_dma
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# hdmi
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@ -107,9 +107,9 @@ set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.2 a
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set_property -dict [list CONFIG.PHY_TYPE {RGMII}] $axi_ethernet
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set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
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set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.C_INCLUDE_MM2S_DRE {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.C_SG_USE_STSAPP_LENGTH {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.C_INCLUDE_S2MM_DRE {1}] $axi_ethernet_dma
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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@ -105,9 +105,9 @@ set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
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# audio peripherals
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@ -97,9 +97,9 @@ set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
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# audio peripherals
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@ -119,9 +119,9 @@ set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
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# audio peripherals
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