Fmcomms1: Initial commit for KC705
Modified common project so it can be compatible for both ARM and Microblaze based systems.main
Adrian Costina
parent
aa7b0bb4dd
commit
2070c66b87
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@ -33,10 +33,12 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
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set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9122_dma_interconnect
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if {$sys_zynq == 1} {
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set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9122_dma_interconnect
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}
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# adc peripherals
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@ -60,25 +62,42 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
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set axi_ad9643_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9643_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9643_dma_interconnect
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if {$sys_zynq == 1} {
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set axi_ad9643_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9643_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9643_dma_interconnect
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}
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# additions to default configuration
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set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect
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set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
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}
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
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}
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# reference clock shared with audio clock
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# foro microblaze based system, add an additional clock to use with the ILA fifo
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set_property -dict [list CONFIG.CLKOUT2_USED {true}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {30}] $sys_audio_clkgen
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.CLKOUT2_USED {true}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {30}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT3_USED {true}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125}] $sys_audio_clkgen
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} else {
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set_property -dict [list CONFIG.CLKOUT2_USED {true}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {30}] $sys_audio_clkgen
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}
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# connections (dac)
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connect_bd_net -net dac_div_clk [get_bd_pins axi_ad9122/dac_div_clk]
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@ -95,7 +114,11 @@ connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_ports dac_data_out_n]
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connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en]
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connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122/dac_ddata_64] [get_bd_pins axi_ad9122_dma/fifo_rd_dout]
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connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
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connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
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if {$sys_zynq == 0 } {
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connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In6]
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} else {
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connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
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}
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# connections (adc)
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@ -120,7 +143,11 @@ connect_bd_net -net axi_ad9643_adc_dovf [get_bd_pins axi_ad9643/adc_dovf
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connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins sys_ad9643_util_wfifo/s_wr] [get_bd_pins axi_ad9643_dma/fifo_wr_en]
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connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_ad9643_util_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din]
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connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_ad9643_util_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow]
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connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2]
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if {$sys_zynq == 0} {
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connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In5]
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} else {
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connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2]
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}
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connect_bd_net -net axi_ad9643_fifo_rst [get_bd_pins sys_ad9643_util_wfifo/fifo_rst] [get_bd_pins sys_ad9643_fifo/rst]
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connect_bd_net -net axi_ad9643_fifo_wr [get_bd_pins sys_ad9643_util_wfifo/fifo_wr] [get_bd_pins sys_ad9643_fifo/wr_en]
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@ -155,40 +182,62 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/s_axi_aresetn]
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# memory interconnects share the same clock (fclk2)
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# for microblaze based system, use the clock only for ILA
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set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
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if {$sys_zynq == 0} {
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set sys_fmc_dma_clk_source [get_bd_pins sys_audio_clkgen/clk_out3]
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source`
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} else {
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set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
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}
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# interconnect (mem/dac)
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connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
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connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
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if {$sys_zynq == 0 } {
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connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_200m_resetn_source
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
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} else {
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connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
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connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
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}
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# interconnect (mem/adc)
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connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
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connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
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if {$sys_zynq == 0 } {
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connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
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} else {
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connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
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connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
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}
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# ila (adc) - need a fifo, zed ila can not run at 250MHz
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@ -207,12 +256,11 @@ set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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set ila_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ila_constant_1]
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connect_bd_net -net axi_ad9643_adc_mon_data [get_bd_pins axi_ad9643/adc_mon_data] [get_bd_pins ila_adc_fifo/din]
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connect_bd_net -net adc_clk [get_bd_pins axi_ad9643/adc_clk] [get_bd_pins ila_adc_fifo/wr_clk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc_fifo/rd_clk]
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connect_bd_net -net xlconstant_0_const [get_bd_pins ila_adc_fifo/rd_en] [get_bd_pins ila_adc_fifo/wr_en] [get_bd_pins ila_constant_1/const]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc_fifo/rd_clk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk]
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connect_bd_net -net ila_adc_fifo_dout [get_bd_pins ila_adc_fifo/dout] [get_bd_pins ila_adc/probe0]
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@ -222,11 +270,15 @@ connect_bd_net -net fmcomms1_ref_clk [get_bd_pins sys_audio_clkgen/clk_out2] [ge
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# address map
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create_bd_addr_seg -range 0x00010000 -offset 0x74200000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122
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create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma
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create_bd_addr_seg -range 0x00010000 -offset 0x79020000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643
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create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma
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|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x74200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
} else {
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
|
||||
source ../common/fmcomms1_bd.tcl
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
|
||||
# reference
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N
|
||||
|
||||
# dac
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN AG28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P
|
||||
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P
|
||||
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P
|
||||
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N
|
||||
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P
|
||||
set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N
|
||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P
|
||||
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N
|
||||
set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N
|
||||
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN AF26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N
|
||||
|
||||
# adc
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P
|
||||
set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N
|
||||
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AC25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AH20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
|
||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N
|
||||
set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AK24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P
|
||||
set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
|
||||
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
|
||||
create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
|
||||
create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
|
||||
|
||||
set_clock_groups -asynchronous -group {dac_div_clk}
|
||||
set_clock_groups -asynchronous -group {adc_clk}
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
adi_project_create fmcomms1_kc705
|
||||
adi_project_files fmcomms1_kc705 [list \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
|
||||
|
||||
adi_project_run fmcomms1_kc705
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,288 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
sys_rst,
|
||||
sys_clk_p,
|
||||
sys_clk_n,
|
||||
|
||||
uart_sin,
|
||||
uart_sout,
|
||||
|
||||
ddr3_1_n,
|
||||
ddr3_1_p,
|
||||
ddr3_reset_n,
|
||||
ddr3_addr,
|
||||
ddr3_ba,
|
||||
ddr3_cas_n,
|
||||
ddr3_ras_n,
|
||||
ddr3_we_n,
|
||||
ddr3_ck_n,
|
||||
ddr3_ck_p,
|
||||
ddr3_cke,
|
||||
ddr3_cs_n,
|
||||
ddr3_dm,
|
||||
ddr3_dq,
|
||||
ddr3_dqs_n,
|
||||
ddr3_dqs_p,
|
||||
ddr3_odt,
|
||||
|
||||
mdio_mdc,
|
||||
mdio_mdio_io,
|
||||
mii_rst_n,
|
||||
mii_col,
|
||||
mii_crs,
|
||||
mii_rx_clk,
|
||||
mii_rx_er,
|
||||
mii_rx_dv,
|
||||
mii_rxd,
|
||||
mii_tx_clk,
|
||||
mii_tx_en,
|
||||
mii_txd,
|
||||
|
||||
fan_pwm,
|
||||
|
||||
gpio_lcd,
|
||||
gpio_led,
|
||||
gpio_sw,
|
||||
|
||||
iic_rstn,
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
dac_clk_in_p,
|
||||
dac_clk_in_n,
|
||||
dac_clk_out_p,
|
||||
dac_clk_out_n,
|
||||
dac_frame_out_p,
|
||||
dac_frame_out_n,
|
||||
dac_data_out_p,
|
||||
dac_data_out_n,
|
||||
|
||||
adc_clk_in_p,
|
||||
adc_clk_in_n,
|
||||
adc_or_in_p,
|
||||
adc_or_in_n,
|
||||
adc_data_in_p,
|
||||
adc_data_in_n,
|
||||
|
||||
ref_clk_out_p,
|
||||
ref_clk_out_n,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_hsync,
|
||||
hdmi_vsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
spdif);
|
||||
|
||||
input sys_rst;
|
||||
input sys_clk_p;
|
||||
input sys_clk_n;
|
||||
|
||||
input uart_sin;
|
||||
output uart_sout;
|
||||
|
||||
output [ 2:0] ddr3_1_n;
|
||||
output [ 1:0] ddr3_1_p;
|
||||
output ddr3_reset_n;
|
||||
output [13:0] ddr3_addr;
|
||||
output [ 2:0] ddr3_ba;
|
||||
output ddr3_cas_n;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_we_n;
|
||||
output [ 0:0] ddr3_ck_n;
|
||||
output [ 0:0] ddr3_ck_p;
|
||||
output [ 0:0] ddr3_cke;
|
||||
output [ 0:0] ddr3_cs_n;
|
||||
output [ 7:0] ddr3_dm;
|
||||
inout [63:0] ddr3_dq;
|
||||
inout [ 7:0] ddr3_dqs_n;
|
||||
inout [ 7:0] ddr3_dqs_p;
|
||||
output [ 0:0] ddr3_odt;
|
||||
|
||||
output mdio_mdc;
|
||||
inout mdio_mdio_io;
|
||||
output mii_rst_n;
|
||||
input mii_col;
|
||||
input mii_crs;
|
||||
input mii_rx_clk;
|
||||
input mii_rx_er;
|
||||
input mii_rx_dv;
|
||||
input [ 3:0] mii_rxd;
|
||||
input mii_tx_clk;
|
||||
output mii_tx_en;
|
||||
output [ 3:0] mii_txd;
|
||||
|
||||
output fan_pwm;
|
||||
|
||||
inout [ 6:0] gpio_lcd;
|
||||
inout [ 7:0] gpio_led;
|
||||
inout [ 8:0] gpio_sw;
|
||||
|
||||
output iic_rstn;
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input dac_clk_in_p;
|
||||
input dac_clk_in_n;
|
||||
output dac_clk_out_p;
|
||||
output dac_clk_out_n;
|
||||
output dac_frame_out_p;
|
||||
output dac_frame_out_n;
|
||||
output [15:0] dac_data_out_p;
|
||||
output [15:0] dac_data_out_n;
|
||||
|
||||
input adc_clk_in_p;
|
||||
input adc_clk_in_n;
|
||||
input adc_or_in_p;
|
||||
input adc_or_in_n;
|
||||
input [13:0] adc_data_in_p;
|
||||
input [13:0] adc_data_in_n;
|
||||
|
||||
output ref_clk_out_p;
|
||||
output ref_clk_out_n;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_hsync;
|
||||
output hdmi_vsync;
|
||||
output hdmi_data_e;
|
||||
output [15:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
wire ref_clk;
|
||||
wire oddr_ref_clk;
|
||||
|
||||
// instantiations
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE"),
|
||||
.INIT (1'b0),
|
||||
.SRTYPE ("ASYNC"))
|
||||
i_oddr_ref_clk (
|
||||
.S (1'b0),
|
||||
.CE (1'b1),
|
||||
.R (1'b0),
|
||||
.C (ref_clk),
|
||||
.D1 (1'b1),
|
||||
.D2 (1'b0),
|
||||
.Q (oddr_ref_clk));
|
||||
|
||||
OBUFDS i_obufds_ref_clk (
|
||||
.I (oddr_ref_clk),
|
||||
.O (ref_clk_out_p),
|
||||
.OB (ref_clk_out_n));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr3_1_n (ddr3_1_n),
|
||||
.ddr3_1_p (ddr3_1_p),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
.ddr3_ck_n (ddr3_ck_n),
|
||||
.ddr3_ck_p (ddr3_ck_p),
|
||||
.ddr3_cke (ddr3_cke),
|
||||
.ddr3_cs_n (ddr3_cs_n),
|
||||
.ddr3_dm (ddr3_dm),
|
||||
.ddr3_dq (ddr3_dq),
|
||||
.ddr3_dqs_n (ddr3_dqs_n),
|
||||
.ddr3_dqs_p (ddr3_dqs_p),
|
||||
.ddr3_odt (ddr3_odt),
|
||||
.ddr3_ras_n (ddr3_ras_n),
|
||||
.ddr3_reset_n (ddr3_reset_n),
|
||||
.ddr3_we_n (ddr3_we_n),
|
||||
.fan_pwm (fan_pwm),
|
||||
.gpio_lcd_tri_io (gpio_lcd),
|
||||
.gpio_led_tri_io (gpio_led),
|
||||
.gpio_sw_tri_io (gpio_sw),
|
||||
.adc_clk_in_n (adc_clk_in_n),
|
||||
.adc_clk_in_p (adc_clk_in_p),
|
||||
.adc_data_in_n (adc_data_in_n),
|
||||
.adc_data_in_p (adc_data_in_p),
|
||||
.adc_or_in_n (adc_or_in_n),
|
||||
.adc_or_in_p (adc_or_in_p),
|
||||
.dac_clk_in_n (dac_clk_in_n),
|
||||
.dac_clk_in_p (dac_clk_in_p),
|
||||
.dac_clk_out_n (dac_clk_out_n),
|
||||
.dac_clk_out_p (dac_clk_out_p),
|
||||
.dac_data_out_n (dac_data_out_n),
|
||||
.dac_data_out_p (dac_data_out_p),
|
||||
.dac_frame_out_n (dac_frame_out_n),
|
||||
.dac_frame_out_p (dac_frame_out_p),
|
||||
.ref_clk (ref_clk),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.iic_rstn (iic_rstn),
|
||||
.mdio_mdc (mdio_mdc),
|
||||
.mdio_mdio_io (mdio_mdio_io),
|
||||
.mii_col (mii_col),
|
||||
.mii_crs (mii_crs),
|
||||
.mii_rst_n (mii_rst_n),
|
||||
.mii_rx_clk (mii_rx_clk),
|
||||
.mii_rx_dv (mii_rx_dv),
|
||||
.mii_rx_er (mii_rx_er),
|
||||
.mii_rxd (mii_rxd),
|
||||
.mii_tx_clk (mii_tx_clk),
|
||||
.mii_tx_en (mii_tx_en),
|
||||
.mii_txd (mii_txd),
|
||||
.spdif (spdif),
|
||||
.sys_clk_n (sys_clk_n),
|
||||
.sys_clk_p (sys_clk_p),
|
||||
.sys_rst (sys_rst),
|
||||
.uart_sin (uart_sin),
|
||||
.uart_sout (uart_sout),
|
||||
.unc_int0 (1'b0),
|
||||
.unc_int1 (1'b0),
|
||||
.unc_int2 (1'b0),
|
||||
.unc_int3 (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue