diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
index a452e5652..9f277d7a3 100644
--- a/library/axi_dmac/request_arb.v
+++ b/library/axi_dmac/request_arb.v
@@ -596,16 +596,16 @@ end endgenerate
 
 generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
 
+wire [ID_WIDTH-1:0] src_data_id;
+wire [ID_WIDTH-1:0] src_address_id;
+wire src_address_eot = eot_mem_src[src_address_id];
+
 assign source_id = src_address_id;
 assign source_eot = src_address_eot;
 
 assign src_clk = m_src_axi_aclk;
 assign src_ext_resetn = m_src_axi_aresetn;
 
-wire [ID_WIDTH-1:0] src_data_id;
-wire [ID_WIDTH-1:0] src_address_id;
-wire src_address_eot = eot_mem_src[src_address_id];
-
 assign dbg_src_address_id = src_address_id;
 assign dbg_src_data_id = src_data_id;
 
@@ -780,14 +780,14 @@ end
 
 if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
 
+wire src_eot = eot_mem_src[src_response_id];
+
 assign source_id = src_response_id;
 assign source_eot = src_eot;
 
 assign src_clk = fifo_wr_clk;
 assign src_ext_resetn = 1'b1;
 
-wire src_eot = eot_mem_src[src_response_id];
-
 assign dbg_src_address_id = 'h00;
 assign dbg_src_data_id = 'h00;
 
diff --git a/library/axi_dmac/tb/dma_read_shutdown_tb b/library/axi_dmac/tb/dma_read_shutdown_tb
index bf7da0737..6ba47d32d 100755
--- a/library/axi_dmac/tb/dma_read_shutdown_tb
+++ b/library/axi_dmac/tb/dma_read_shutdown_tb
@@ -8,9 +8,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
 SOURCE+=" ../dest_fifo_inf.v"
+SOURCE+=" ../axi_dmac_response_manager.v"
 SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
 SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
 SOURCE+=" ../../util_cdc/sync_bits.v"
+SOURCE+=" ../../util_cdc/sync_event.v"
 SOURCE+=" ../../common/ad_mem.v"
 
 cd `dirname $0`
diff --git a/library/axi_dmac/tb/dma_read_tb b/library/axi_dmac/tb/dma_read_tb
index 7fb81852b..7378f36ed 100755
--- a/library/axi_dmac/tb/dma_read_tb
+++ b/library/axi_dmac/tb/dma_read_tb
@@ -7,9 +7,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
 SOURCE+=" ../dest_fifo_inf.v"
+SOURCE+=" ../axi_dmac_response_manager.v"
 SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
 SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
 SOURCE+=" ../../util_cdc/sync_bits.v"
+SOURCE+=" ../../util_cdc/sync_event.v"
 SOURCE+=" ../../common/ad_mem.v"
 
 cd `dirname $0`
diff --git a/library/axi_dmac/tb/dma_write_shutdown_tb b/library/axi_dmac/tb/dma_write_shutdown_tb
index cc250e5c6..5fdb11f79 100755
--- a/library/axi_dmac/tb/dma_write_shutdown_tb
+++ b/library/axi_dmac/tb/dma_write_shutdown_tb
@@ -8,9 +8,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"
 SOURCE+=" ../src_fifo_inf.v"
+SOURCE+=" ../axi_dmac_response_manager.v"
 SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
 SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
 SOURCE+=" ../../util_cdc/sync_bits.v"
+SOURCE+=" ../../util_cdc/sync_event.v"
 SOURCE+=" ../../common/ad_mem.v"
 
 cd `dirname $0`
diff --git a/library/axi_dmac/tb/dma_write_shutdown_tb.v b/library/axi_dmac/tb/dma_write_shutdown_tb.v
index 26d9f1c3c..af0379087 100644
--- a/library/axi_dmac/tb/dma_write_shutdown_tb.v
+++ b/library/axi_dmac/tb/dma_write_shutdown_tb.v
@@ -144,6 +144,7 @@ module dmac_dma_write_shutdown_tb;
     .ctrl_pause(1'b0),
 
     .req_eot(),
+    .req_response_ready(1'b1),
 
     .req_valid(1'b1),
     .req_ready(),
diff --git a/library/axi_dmac/tb/dma_write_tb b/library/axi_dmac/tb/dma_write_tb
index de24fdceb..8538ac083 100755
--- a/library/axi_dmac/tb/dma_write_tb
+++ b/library/axi_dmac/tb/dma_write_tb
@@ -7,9 +7,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"
 SOURCE+=" ../src_fifo_inf.v"
+SOURCE+=" ../axi_dmac_response_manager.v"
 SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
 SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
 SOURCE+=" ../../util_cdc/sync_bits.v"
+SOURCE+=" ../../util_cdc/sync_event.v"
 SOURCE+=" ../../common/ad_mem.v"
 
 cd `dirname $0`
diff --git a/library/axi_dmac/tb/dma_write_tb.v b/library/axi_dmac/tb/dma_write_tb.v
index 0dfc9fda9..90164525b 100644
--- a/library/axi_dmac/tb/dma_write_tb.v
+++ b/library/axi_dmac/tb/dma_write_tb.v
@@ -132,6 +132,7 @@ module dmac_dma_write_tb;
     .ctrl_pause(1'b0),
 
     .req_eot(eot),
+    .req_response_ready(1'b1),
 
     .req_valid(req_valid),
     .req_ready(req_ready),
diff --git a/library/axi_dmac/tb/regmap_tb b/library/axi_dmac/tb/regmap_tb
index a80284106..b2467157c 100755
--- a/library/axi_dmac/tb/regmap_tb
+++ b/library/axi_dmac/tb/regmap_tb
@@ -3,6 +3,8 @@
 SOURCE="regmap_tb.v"
 SOURCE+=" ../axi_dmac_regmap.v ../axi_dmac_regmap_request.v"
 SOURCE+=" ../../common/up_axi.v"
+SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
+SOURCE+=" ../../util_axis_fifo/address_sync.v"
 
 cd `dirname $0`
 source run_tb.sh
diff --git a/library/axi_dmac/tb/regmap_tb.v b/library/axi_dmac/tb/regmap_tb.v
index dccec4161..1ab42df5e 100644
--- a/library/axi_dmac/tb/regmap_tb.v
+++ b/library/axi_dmac/tb/regmap_tb.v
@@ -42,13 +42,14 @@ module dmac_regmap_tb;
   `include "tb_base.v"
 
   localparam DMA_LENGTH_WIDTH = 24;
+  localparam DMA_LENGTH_ALIGN = 3;
   localparam BYTES_PER_BEAT = 1;
   localparam DMA_AXI_ADDR_WIDTH = 32;
 
   localparam LENGTH_ALIGN = 2;
   localparam LENGTH_MASK = {DMA_LENGTH_WIDTH{1'b1}};
   localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}};
-  localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}}
+  localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
   localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
 
   localparam VAL_DBG_SRC_ADDR = 32'h76543210;