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axi_dmac: component level testbench updates

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Laszlo Nagy 2018-08-30 20:34:53 +01:00 committed by Laszlo Nagy
parent a4c4e384bb
commit 20ac7dcaef
9 changed files with 20 additions and 7 deletions
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12
library/axi_dmac/request_arb.v
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@ -596,16 +596,16 @@ end endgenerate
generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
wire [ID_WIDTH-1:0] src_data_id;
wire [ID_WIDTH-1:0] src_address_id;
wire src_address_eot = eot_mem_src[src_address_id];
assign source_id = src_address_id;
assign source_eot = src_address_eot;
assign src_clk = m_src_axi_aclk;
assign src_ext_resetn = m_src_axi_aresetn;
wire [ID_WIDTH-1:0] src_data_id;
wire [ID_WIDTH-1:0] src_address_id;
wire src_address_eot = eot_mem_src[src_address_id];
assign dbg_src_address_id = src_address_id;
assign dbg_src_data_id = src_data_id;
@ -780,14 +780,14 @@ end
if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
wire src_eot = eot_mem_src[src_response_id];
assign source_id = src_response_id;
assign source_eot = src_eot;
assign src_clk = fifo_wr_clk;
assign src_ext_resetn = 1'b1;
wire src_eot = eot_mem_src[src_response_id];
assign dbg_src_address_id = 'h00;
assign dbg_src_data_id = 'h00;

2
library/axi_dmac/tb/dma_read_shutdown_tb
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@ -8,9 +8,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
SOURCE+=" ../dest_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem.v"
cd `dirname $0`

2
library/axi_dmac/tb/dma_read_tb
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@ -7,9 +7,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
SOURCE+=" ../dest_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem.v"
cd `dirname $0`

2
library/axi_dmac/tb/dma_write_shutdown_tb
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@ -8,9 +8,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../src_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem.v"
cd `dirname $0`

1
library/axi_dmac/tb/dma_write_shutdown_tb.v
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@ -144,6 +144,7 @@ module dmac_dma_write_shutdown_tb;
.ctrl_pause(1'b0),
.req_eot(),
.req_response_ready(1'b1),
.req_valid(1'b1),
.req_ready(),

2
library/axi_dmac/tb/dma_write_tb
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@ -7,9 +7,11 @@ SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../src_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem.v"
cd `dirname $0`

1
library/axi_dmac/tb/dma_write_tb.v
View File

@ -132,6 +132,7 @@ module dmac_dma_write_tb;
.ctrl_pause(1'b0),
.req_eot(eot),
.req_response_ready(1'b1),
.req_valid(req_valid),
.req_ready(req_ready),

2
library/axi_dmac/tb/regmap_tb
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@ -3,6 +3,8 @@
SOURCE="regmap_tb.v"
SOURCE+=" ../axi_dmac_regmap.v ../axi_dmac_regmap_request.v"
SOURCE+=" ../../common/up_axi.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_axis_fifo/address_sync.v"
cd `dirname $0`
source run_tb.sh

3
library/axi_dmac/tb/regmap_tb.v
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@ -42,13 +42,14 @@ module dmac_regmap_tb;
`include "tb_base.v"
localparam DMA_LENGTH_WIDTH = 24;
localparam DMA_LENGTH_ALIGN = 3;
localparam BYTES_PER_BEAT = 1;
localparam DMA_AXI_ADDR_WIDTH = 32;
localparam LENGTH_ALIGN = 2;
localparam LENGTH_MASK = {DMA_LENGTH_WIDTH{1'b1}};
localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}};
localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}}
localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
localparam VAL_DBG_SRC_ADDR = 32'h76543210;