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iodelay: Expose the REFCLK_FREQUENCY parameter

main
Istvan Csomortani 2019-06-05 15:23:46 +03:00 committed by István Csomortáni
parent 993497438b
commit 20b0c92a1f
14 changed files with 85 additions and 46 deletions
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9
library/axi_ad9265/axi_ad9265_if.v
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@ -40,7 +40,8 @@
module axi_ad9265_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
@ -100,7 +101,8 @@ module axi_ad9265_if #(
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
@ -122,7 +124,8 @@ module axi_ad9265_if #(
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),

9
library/axi_ad9361/axi_ad9361.v
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@ -65,7 +65,8 @@ module axi_ad9361 #(
parameter DAC_USERPORTS_DISABLE = 0,
parameter DAC_IQCORRECTION_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter MIMO_ENABLE = 0) (
parameter MIMO_ENABLE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// physical interface (receive-lvds)
@ -331,7 +332,8 @@ module axi_ad9361 #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.CLK_DESKEW (MIMO_ENABLE))
.CLK_DESKEW (MIMO_ENABLE),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_dev_if (
.rx_clk_in (rx_clk_in),
.rx_frame_in (rx_frame_in),
@ -393,7 +395,8 @@ module axi_ad9361 #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.CLK_DESKEW (MIMO_ENABLE))
.CLK_DESKEW (MIMO_ENABLE),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_dev_if (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),

24
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
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@ -40,7 +40,8 @@ module axi_ad9361_cmos_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter CLK_DESKEW = 0) (
parameter CLK_DESKEW = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// physical interface (receive)
@ -435,7 +436,8 @@ module axi_ad9361_cmos_if #(
.SINGLE_ENDED (1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_data (
.rx_clk (l_clk),
.rx_data_in_p (rx_data_in[i]),
@ -458,7 +460,8 @@ module axi_ad9361_cmos_if #(
.SINGLE_ENDED (1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_frame (
.rx_clk (l_clk),
.rx_data_in_p (rx_frame_in),
@ -482,7 +485,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_data_1[i]),
@ -506,7 +510,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_frame[1]),
@ -528,7 +533,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (tx_clk[1]),
@ -550,7 +556,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_int_p),
@ -572,7 +579,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_int_p),

24
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -40,7 +40,8 @@ module axi_ad9361_lvds_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter CLK_DESKEW = 0) (
parameter CLK_DESKEW = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// physical interface (receive)
@ -533,7 +534,8 @@ module axi_ad9361_lvds_if #(
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_data (
.rx_clk (l_clk),
.rx_data_in_p (rx_data_in_p[i]),
@ -555,7 +557,8 @@ module axi_ad9361_lvds_if #(
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_frame (
.rx_clk (l_clk),
.rx_data_in_p (rx_frame_in_p),
@ -578,7 +581,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_data_1[i]),
@ -601,7 +605,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_frame),
@ -622,7 +627,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (tx_clk[1]),
@ -644,7 +650,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_int_p),
@ -666,7 +673,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_int_p),

8
library/axi_ad9467/axi_ad9467.v
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@ -37,12 +37,13 @@
module axi_ad9467#(
parameter ID = 0,
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
// physical interface
@ -148,7 +149,8 @@ module axi_ad9467#(
axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),

9
library/axi_ad9467/axi_ad9467_if.v
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@ -39,7 +39,8 @@
module axi_ad9467_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
// adc interface (clk, data, over-range)
@ -130,7 +131,8 @@ module axi_ad9467_if #(
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
@ -152,7 +154,8 @@ module axi_ad9467_if #(
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),

6
library/axi_ad9625/axi_ad9625.v
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@ -41,7 +41,8 @@ module axi_ad9625 #(
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
parameter DEV_PACKAGE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// jesd interface
// rx_clk is (line-rate/40)
@ -142,7 +143,8 @@ module axi_ad9625 #(
assign adc_valid = 1'b1;
axi_ad9625_if #(
.ID (ID))
.ID (ID),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_if (
.rx_clk (rx_clk),
.rx_sof (rx_sof),

6
library/axi_ad9963/axi_ad9963.v
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@ -55,7 +55,8 @@ module axi_ad9963 #(
parameter ADC_DATAFORMAT_DISABLE = 0,
parameter ADC_DCFILTER_DISABLE = 0,
parameter ADC_IQCORRECTION_DISABLE = 0,
parameter ADC_SCALECORRECTION_ONLY = 1) (
parameter ADC_SCALECORRECTION_ONLY = 1,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// physical interface (receive)
@ -182,7 +183,8 @@ module axi_ad9963 #(
axi_ad9963_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_dev_if (
.trx_clk (trx_clk),
.trx_iq (trx_iq),

6
library/axi_ad9963/axi_ad9963_if.v
View File

@ -41,7 +41,8 @@ module axi_ad9963_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter ADC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
// physical interface (receive)
@ -156,7 +157,8 @@ module axi_ad9963_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_data (
.rx_clk (adc_clk),
.rx_data_in_p (trx_data[l_inst]),

6
library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
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@ -44,7 +44,8 @@ module axi_fmcadc5_sync #(
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0) (
parameter [ 7:0] DEV_PACKAGE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// receive interface
@ -768,7 +769,8 @@ module axi_fmcadc5_sync #(
.SINGLE_ENDED (0),
.IODELAY_ENABLE (1),
.IODELAY_CTRL (1),
.IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"))
.IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_sysref (
.tx_clk (rx_clk),
.tx_data_p (rx_sysref_e),

7
library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
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@ -43,7 +43,8 @@ module util_gmii_to_rgmii #(
parameter PHY_AD = 5'b10000,
parameter IODELAY_CTRL = 1'b0,
parameter IDELAY_VALUE = 18,
parameter IODELAY_GROUP = "if_delay_group") (
parameter IODELAY_GROUP = "if_delay_group",
parameter REFCLK_FREQUENCY = 200) (
input clk_20m,
input clk_25m,
@ -214,7 +215,7 @@ module util_gmii_to_rgmii #(
IDELAYE2 #(
.IDELAY_TYPE("FIXED"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.REFCLK_FREQUENCY(200.0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA"),
.IDELAY_VALUE (IDELAY_VALUE),
.DELAY_SRC("IDATAIN")
@ -238,7 +239,7 @@ module util_gmii_to_rgmii #(
IDELAYE2 #(
.IDELAY_TYPE("FIXED"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.REFCLK_FREQUENCY(200.0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA"),
.IDELAY_VALUE (IDELAY_VALUE),
.DELAY_SRC("IDATAIN")

7
library/xilinx/common/ad_data_in.v
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@ -43,7 +43,8 @@ module ad_data_in #(
parameter FPGA_TECHNOLOGY = 0,
parameter IODELAY_ENABLE = 1,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
parameter IODELAY_GROUP = "dev_if_delay_group",
parameter REFCLK_FREQUENCY = 200) (
// data interface
@ -127,7 +128,7 @@ module ad_data_in #(
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
@ -154,7 +155,7 @@ module ad_data_in #(
.SIM_DEVICE (IODELAY_SIM_DEVICE),
.DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.DELAY_FORMAT ("COUNT"))
i_rx_data_idelay (
.CASC_RETURN (1'b0),

5
library/xilinx/common/ad_data_out.v
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@ -41,7 +41,8 @@ module ad_data_out #(
parameter SINGLE_ENDED = 0,
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
parameter IODELAY_GROUP = "dev_if_delay_group",
parameter REFCLK_FREQUENCY = 200) (
// data interface
@ -133,7 +134,7 @@ module ad_data_out #(
.HIGH_PERFORMANCE_MODE ("FALSE"),
.ODELAY_TYPE ("VAR_LOAD"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_tx_data_odelay (

5
library/xilinx/common/ad_serdes_in.v
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@ -42,7 +42,8 @@ module ad_serdes_in #(
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
parameter IODELAY_GROUP = "dev_if_delay_group",
parameter REFCLK_FREQUENCY = 200) (
// reset and clocks
@ -123,7 +124,7 @@ module ad_serdes_in #(
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_idelay (