From 20b89ddd99d1619d68959889a0208cd62f02e6d8 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 20 May 2022 14:39:38 +0100 Subject: [PATCH] ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable --- .../ad9081_fmca_ebz/vcu128/system_constr.xdc | 16 ++--- projects/ad9081_fmca_ebz/vcu128/system_top.v | 66 ++++++++++++------- 2 files changed, 52 insertions(+), 30 deletions(-) diff --git a/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc b/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc index 01bafef7c..8a52236a4 100644 --- a/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc +++ b/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc @@ -48,14 +48,14 @@ set_property -quiet -dict {PACKAGE_PIN AY47 set_property -quiet -dict {PACKAGE_PIN AY46 } [get_ports tx_data_p[4] ] ; ## MGTYTXP0_125 FPGA_SERDOUT_6_P set_property -quiet -dict {PACKAGE_PIN BA45 } [get_ports tx_data_n[3] ] ; ## MGTYTXN3_124 FPGA_SERDOUT_7_N set_property -quiet -dict {PACKAGE_PIN BA44 } [get_ports tx_data_p[3] ] ; ## MGTYTXP3_124 FPGA_SERDOUT_7_P -set_property -quiet -dict {PACKAGE_PIN K22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[0] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_72 -set_property -quiet -dict {PACKAGE_PIN L23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[0] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_72 -set_property -quiet -dict {PACKAGE_PIN A26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[1] ] ; ## IO_L23N_T3U_N9_72 -set_property -quiet -dict {PACKAGE_PIN B27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[1] ] ; ## IO_L23P_T3U_N8_72 -set_property -quiet -dict {PACKAGE_PIN F25 IOSTANDARD LVDS } [get_ports fpga_syncout_n[0] ] ; ## IO_L14N_T2L_N3_GC_72 -set_property -quiet -dict {PACKAGE_PIN F26 IOSTANDARD LVDS } [get_ports fpga_syncout_p[0] ] ; ## IO_L14P_T2L_N2_GC_72 -set_property -quiet -dict {PACKAGE_PIN D22 IOSTANDARD LVDS } [get_ports fpga_syncout_n[1] ] ; ## IO_L15N_T2L_N5_AD11N_72 -set_property -quiet -dict {PACKAGE_PIN E22 IOSTANDARD LVDS } [get_ports fpga_syncout_p[1] ] ; ## IO_L15P_T2L_N4_AD11P_72 +set_property -quiet -dict {PACKAGE_PIN K22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_0_n ] ; ## IO_L4N_T0U_N7_DBC_AD7N_72 +set_property -quiet -dict {PACKAGE_PIN L23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_0_p ] ; ## IO_L4P_T0U_N6_DBC_AD7P_72 +set_property -quiet -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## IO_L23N_T3U_N9_72 +set_property -quiet -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## IO_L23P_T3U_N8_72 +set_property -quiet -dict {PACKAGE_PIN F25 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## IO_L14N_T2L_N3_GC_72 +set_property -quiet -dict {PACKAGE_PIN F26 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## IO_L14P_T2L_N2_GC_72 +set_property -quiet -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## IO_L15N_T2L_N5_AD11N_72 +set_property -quiet -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## IO_L15P_T2L_N4_AD11P_72 set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L6P_T0U_N10_AD6P_72 set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L6N_T0U_N11_AD6N_72 set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L21P_T3L_N4_AD8P_71 diff --git a/projects/ad9081_fmca_ebz/vcu128/system_top.v b/projects/ad9081_fmca_ebz/vcu128/system_top.v index d2d282b4e..dcef79b29 100644 --- a/projects/ad9081_fmca_ebz/vcu128/system_top.v +++ b/projects/ad9081_fmca_ebz/vcu128/system_top.v @@ -40,7 +40,9 @@ module system_top #( parameter TX_JESD_L = 8, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 8, - parameter RX_NUM_LINKS = 1 + parameter RX_NUM_LINKS = 1, + parameter JESD_MODE = "8B10B" + ) ( input sys_rst, @@ -97,10 +99,14 @@ module system_top #( input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, - input [TX_NUM_LINKS-1:0] fpga_syncin_n, - input [TX_NUM_LINKS-1:0] fpga_syncin_p, - output [RX_NUM_LINKS-1:0] fpga_syncout_n, - output [RX_NUM_LINKS-1:0] fpga_syncout_p, + input fpga_syncin_0_n, + input fpga_syncin_0_p, + inout fpga_syncin_1_n, + inout fpga_syncin_1_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, inout [10:0] gpio, inout hmc_gpio1, output hmc_sync, @@ -169,22 +175,15 @@ module system_top #( .CEB(1'b0), .ODIV2 (clkin8)); - genvar i; - generate - for(i=0;i 1 & JESD_MODE == "8B10B") begin + assign tx_syncin[1] = fpga_syncin_1_p; + end else begin + ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf ( + .dio_t (gpio_t[61:60]), + .dio_i (gpio_o[61:60]), + .dio_o (gpio_i[61:60]), + .dio_p ({fpga_syncin_1_n, // 61 + fpga_syncin_1_p})); // 60 + end + + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate ad_iobuf #(.DATA_WIDTH(8)) i_iobuf_bd ( .dio_t (gpio_t[7:0]), @@ -250,7 +272,7 @@ module system_top #( .dio_o (gpio_i[7:0]), .dio_p (gpio_bd)); - assign gpio_i[63:54] = gpio_o[63:54]; + assign gpio_i[59:54] = gpio_o[59:54]; assign gpio_i[31:8] = gpio_o[31:8]; system_wrapper i_system_wrapper (