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util_cpack2: Update hw.tcl file

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Istvan Csomortani 2019-08-21 13:33:18 +03:00 committed by István Csomortáni
parent bc2f916dfc
commit 20dd17aa07
1 changed files with 9 additions and 9 deletions
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18
library/util_pack/util_cpack2/util_cpack2_hw.tcl
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@ -72,17 +72,17 @@ proc util_cpack_elab {} {
ad_interface signal fifo_wr_overflow output 1 ovf ad_interface signal fifo_wr_overflow output 1 ovf
for {set n 0} {$n < $num_channels} {incr n} { for {set n 0} {$n < $num_channels} {incr n} {
add_interface adc_ch_${n} conduit end add_interface adc_ch_$n conduit end
add_interface_port adc_ch_${n} enable_${n} enable Input 1 add_interface_port adc_ch_$n enable_$n enable Input 1
set_port_property enable_${n} fragment_list "enable(${n}:${n})" set_port_property enable_$n fragment_list [format "enable(%d:%d)" $n $n]
add_interface_port adc_ch_${n} fifo_wr_en_${n} valid Input 1 add_interface_port adc_ch_$n fifo_wr_en_$n valid Input 1
set_port_property fifo_wr_en_${n} fragment_list "fifo_wr_en(${n})" set_port_property fifo_wr_en_$n fragment_list [format "fifo_wr_en(%d)" $n]
add_interface_port adc_ch_${n} fifo_wr_data_${n} data Input $channel_data_width add_interface_port adc_ch_$n fifo_wr_data_$n data Input $channel_data_width
set_port_property fifo_wr_data_${n} fragment_list [format "fifo_wr_data(%d:%d)" \ set_port_property fifo_wr_data_$n fragment_list [format "fifo_wr_data(%d:%d)" \
[expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]] [expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]]
set_interface_property adc_ch_${n} associatedClock clk set_interface_property adc_ch_$n associatedClock clk
set_interface_property adc_ch_${n} associatedReset "" set_interface_property adc_ch_$n associatedReset ""
} }
} }