ad_fmclidar1_ebz: Initial commit
This commit was created by squashing the following commits, these
messages were kept just for sake of history:
ad9694_500ebz: Mirror the SPI interface to FMCB
ad9694_500ebz: Set transceiver reference clock to 250
ad9694_500ebz: Allow to configure number of lanes, number of converters
and sample rate
axi_ad9694: Fix number of lanes, it must be 2
ad9694_500ebz: Update the mirrored spi pin assignments
ad9694_500ebz: Gate SPI MISO signals based on chip-select
ad9694_500ebz: Set channel pack sample width
ad9694_500ebz: Change reference clock location
ad9694_500ebz: Remove transceiver memory map arbitration
ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH
ad9694_500ebz: Adjust breakout board pin locations
ad_fmclidar1_ebz: Rename the ad9694_500ebz project
ad_fmclidar1_ebz: Fix lane mapping
ad_fmclidar1_ebz: Delete deprecated files
ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design
ad_fmclidar1_ebz: OTW is an active low signal
ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment
ad_fmclidar1_ebz: Switch to util_adcfifo
ad_fmclidar1_ebz: Enable synced capture for the fifo
ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL
ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB
ad_fmclidar1_ebz: Laser driver runs on ADC's core clock
ad_fmclidar1_ebz_bd: Delete the FIFO instance
Because the DMA transfers are going to be relatively small (< 2kbyte),
the DMA can handle the data rate, even when the frequency of the laser
driver pulse is set to its maximum value. (200 kHz)
The synchronization will be done by connecting the generated pulse to
the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we
need to use the util_axis_syncgen module to make sure that the DMA
catches the pulse, in cases when the pulse width is too narrow. (SYNC is
captures when valid and ready is asserted)
Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's
relative starting point in time fixed, when only 2 or 1 channel is
active.
main
Istvan Csomortani
István Csomortáni
parent
9422da7908
commit
21bbc900c8
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@ -1,7 +1,7 @@
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# ip
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# ip
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source ../scripts/adi_env.tcl
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_laser_driver
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adi_ip_create axi_laser_driver
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adi_ip_files axi_laser_driver [list \
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adi_ip_files axi_laser_driver [list \
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@ -0,0 +1,6 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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@ -0,0 +1,195 @@
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# interfaces and IO ports
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac
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create_bd_port -dir I spi_vco_csn_i
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create_bd_port -dir O spi_vco_csn_o
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create_bd_port -dir I spi_vco_clk_i
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create_bd_port -dir O spi_vco_clk_o
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create_bd_port -dir I spi_vco_sdo_i
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create_bd_port -dir O spi_vco_sdo_o
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create_bd_port -dir I spi_vco_sdi_i
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create_bd_port -dir I spi_afe_adc_csn_i
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create_bd_port -dir O spi_afe_adc_csn_o
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create_bd_port -dir I spi_afe_adc_clk_i
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create_bd_port -dir O spi_afe_adc_clk_o
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create_bd_port -dir I spi_afe_adc_sdo_i
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create_bd_port -dir O spi_afe_adc_sdo_o
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create_bd_port -dir I spi_afe_adc_sdi_i
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create_bd_port -dir O laser_driver
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create_bd_port -dir O laser_driver_en_n
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create_bd_port -dir I laser_driver_otw_n
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# adc peripherals - controlled by PS7/SPI0
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ad_ip_instance axi_adxcvr axi_ad9694_xcvr [list \
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NUM_OF_LANES $NUM_OF_LANES \
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QPLL_ENABLE 1 \
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TX_OR_RX_N 0 \
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]
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adi_axi_jesd204_rx_create ad9694_jesd $NUM_OF_LANES
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adi_tpl_jesd204_rx_create ad9694_tpl_core $NUM_OF_LANES $NUM_OF_CHANNELS $SAMPLES_PER_FRAME $SAMPLE_WIDTH
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ad_ip_instance util_cpack2 util_ad9694_cpack [list \
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NUM_OF_CHANNELS $NUM_OF_CHANNELS \
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SAMPLES_PER_CHANNEL [expr $CHANNEL_DATA_WIDTH / $SAMPLE_WIDTH] \
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SAMPLE_DATA_WIDTH $SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac ad9694_dma [list \
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DMA_TYPE_SRC 1 \
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DMA_TYPE_DEST 0 \
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DMA_DATA_WIDTH_SRC $DMA_DATA_WIDTH \
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DMA_DATA_WIDTH_DEST 64 \
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SYNC_TRANSFER_START 1 \
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FIFO_SIZE 32 \
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]
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# 3-wire SPI for clock synthesizer & VCO - 12.5MHz SCLK rate
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ad_ip_instance axi_quad_spi axi_spi_vco [list \
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C_USE_STARTUP 0 \
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C_NUM_SS_BITS 1 \
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C_SCK_RATIO 8 \
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]
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# I2C for AFE board's DAC
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_IO1_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 1
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# 3-wire SPI for AFE board's ADC - 12.5MHz SCLK rate
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ad_ip_instance axi_quad_spi axi_spi_afe_adc [list \
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C_USE_STARTUP 0 \
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C_NUM_SS_BITS 1 \
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C_SCK_RATIO 8 \
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]
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# shared transceiver core
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ad_ip_instance util_adxcvr util_ad9694_xcvr [list \
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RX_NUM_OF_LANES $NUM_OF_LANES \
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TX_NUM_OF_LANES 0 \
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]
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ad_connect $sys_cpu_resetn util_ad9694_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_ad9694_xcvr/up_clk
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# laser driver - runs in asynchronous mode, using a 250MHz reference clock
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# NOTE: After power up the driver will not generate any pulses, the software
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# must configure the AXI Memory Mapped registers and load the configuration.
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# This is why the parameter PULSE_PERIOD is 0.
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ad_ip_instance axi_laser_driver axi_laser_driver_0 [list \
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ASYNC_CLK_EN 1 \
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PULSE_WIDTH 1 \
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PULSE_PERIOD 0 \
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]
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# a synchronization module, which make sure that the DMA will catch the pulse as
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# its sync signal
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create_bd_cell -type module -reference util_axis_syncgen util_axis_syncgen_0
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set_property -dict [list CONFIG.ASYNC_SYNC {0}] [get_bd_cells util_axis_syncgen_0]
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# reference clocks & resets
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create_bd_port -dir I -type clk rx_ref_clk
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create_bd_port -dir I -type clk rx_device_clk
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ad_xcvrpll rx_ref_clk util_ad9694_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk util_ad9694_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9694_xcvr/up_pll_rst util_ad9694_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9694_xcvr/up_pll_rst util_ad9694_xcvr/up_cpll_rst_*
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# connections (adc)
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ad_xcvrcon util_ad9694_xcvr axi_ad9694_xcvr ad9694_jesd {3 2 0 1} rx_device_clk
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ad_connect rx_device_clk ad9694_tpl_core/link_clk
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ad_connect ad9694_jesd/rx_sof ad9694_tpl_core/link_sof
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ad_connect ad9694_jesd/rx_data_tvalid ad9694_tpl_core/link_valid
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ad_connect ad9694_jesd/rx_data_tdata ad9694_tpl_core/link_data
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ad_connect rx_device_clk util_ad9694_cpack/clk
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for {set i 0} {$i < $NUM_OF_CHANNELS} {incr i} {
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ad_connect ad9694_tpl_core/adc_enable_$i util_ad9694_cpack/enable_$i
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ad_connect ad9694_tpl_core/adc_data_$i util_ad9694_cpack/fifo_wr_data_$i
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}
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ad_connect ad9694_tpl_core/adc_valid_0 util_ad9694_cpack/fifo_wr_en
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ad_connect rx_device_clk ad9694_dma/s_axis_aclk
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ad_connect $sys_cpu_resetn ad9694_dma/m_dest_axi_aresetn
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ad_connect util_ad9694_cpack/packed_fifo_wr_en ad9694_dma/s_axis_valid
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ad_connect util_ad9694_cpack/packed_fifo_wr_data ad9694_dma/s_axis_data
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#ad_connect ad9694_tpl_core/adc_dovf axi_ad9694_fifo/adc_wovf
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ad_connect $sys_cpu_clk axi_spi_vco/ext_spi_clk
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ad_connect spi_vco axi_spi_vco/SPI_0
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ad_connect spi_vco_csn_i axi_spi_vco/ss_i
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ad_connect spi_vco_csn_o axi_spi_vco/ss_o
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ad_connect spi_vco_clk_i axi_spi_vco/sck_i
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ad_connect spi_vco_clk_o axi_spi_vco/sck_o
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ad_connect spi_vco_sdo_i axi_spi_vco/io0_i
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ad_connect spi_vco_sdo_o axi_spi_vco/io0_o
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ad_connect spi_vco_sdi_i axi_spi_vco/io1_i
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ad_connect iic_dac sys_ps7/IIC_1
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ad_connect $sys_cpu_clk axi_spi_afe_adc/ext_spi_clk
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ad_connect spi_afe_adc axi_spi_afe_adc/SPI_0
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ad_connect spi_afe_adc_csn_i axi_spi_afe_adc/ss_i
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ad_connect spi_afe_adc_csn_o axi_spi_afe_adc/ss_o
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ad_connect spi_afe_adc_clk_i axi_spi_afe_adc/sck_i
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ad_connect spi_afe_adc_clk_o axi_spi_afe_adc/sck_o
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ad_connect spi_afe_adc_sdo_i axi_spi_afe_adc/io0_i
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ad_connect spi_afe_adc_sdo_o axi_spi_afe_adc/io0_o
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ad_connect spi_afe_adc_sdi_i axi_spi_afe_adc/io1_i
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# laser driver and sync synchronizer
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ad_connect rx_device_clk axi_laser_driver_0/ext_clk
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ad_connect laser_driver axi_laser_driver_0/driver_pulse
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ad_connect laser_driver_en_n axi_laser_driver_0/driver_en_n
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ad_connect laser_driver_otw_n axi_laser_driver_0/driver_otw_n
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ad_connect axi_laser_driver_0/driver_dp_reset util_ad9694_cpack/reset
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ad_connect rx_device_clk util_axis_syncgen_0/s_axis_aclk
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ad_connect util_axis_syncgen_0/s_axis_aresetn VCC
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ad_connect util_axis_syncgen_0/s_axis_valid util_ad9694_cpack/packed_fifo_wr_en
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ad_connect util_axis_syncgen_0/s_axis_ready VCC
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ad_connect util_axis_syncgen_0/ext_sync axi_laser_driver_0/driver_pulse
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ad_connect util_axis_syncgen_0/s_axis_sync ad9694_dma/s_axis_user
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A50000 axi_ad9694_xcvr
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ad_cpu_interconnect 0x44A10000 ad9694_tpl_core
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ad_cpu_interconnect 0x44AA0000 ad9694_jesd
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ad_cpu_interconnect 0x7c400000 ad9694_dma
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ad_cpu_interconnect 0x7c500000 axi_spi_vco
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ad_cpu_interconnect 0x7c600000 axi_spi_afe_adc
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ad_cpu_interconnect 0x7c700000 axi_laser_driver_0
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9694_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk ad9694_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-11 mb-14 ad9694_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 ad9694_dma/irq
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ad_cpu_interrupt ps-10 mb-15 axi_spi_vco/ip2intc_irpt
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ad_cpu_interrupt ps-9 mb-8 axi_spi_afe_adc/ip2intc_irpt
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ad_cpu_interrupt ps-8 mb-7 axi_laser_driver_0/irq
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@ -0,0 +1,29 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad_fmclidar1_ebz_zc706
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M_DEPS += ../common/util_tia_chsel.v
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M_DEPS += ../common/util_axis_syncgen.v
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M_DEPS += ../common/ad_fmclidar1_ebz_bd.tcl
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M_DEPS += ../../common/zc706/zc706_system_constr.xdc
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M_DEPS += ../../common/zc706/zc706_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/util_cdc/sync_bits.v
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_laser_driver
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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include ../../scripts/project-xilinx.mk
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@ -0,0 +1,25 @@
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# Configurable parameters
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set SAMPLE_RATE_MHZ 1000.0
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set NUM_OF_CHANNELS 4 ; # M
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set SAMPLES_PER_FRAME 1 ; # S
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set NUM_OF_LANES 4 ; # L
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set ADC_RESOLUTION 8 ; # N & NP
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# Auto-computed parameters
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set CHANNEL_DATA_WIDTH [expr 32 * $NUM_OF_LANES / $NUM_OF_CHANNELS]
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set ADC_DATA_WIDTH [expr $CHANNEL_DATA_WIDTH * $NUM_OF_CHANNELS]
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set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH < 128 ? $ADC_DATA_WIDTH : 128]
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set SAMPLE_WIDTH [expr $ADC_RESOLUTION > 8 ? 16 : 8]
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# add RTL sources which will be instantiated in system_bd directly
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adi_project_files ad_fmclidar1_ebz_zc706 [list \
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"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
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"$ad_hdl_dir/library/common/util_axis_syncgen.v" ]
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# source all the block designs
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source ../common/ad_fmclidar1_ebz_bd.tcl
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# ADC digital interface (JESD204B)
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set_property -dict {PACKAGE_PIN AD10 } [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
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set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
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set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_device_clk_p] ; ## D08 FMC_HPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_device_clk_n] ; ## D09 FMC_HPC_LA01_CC_N
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||||||
|
set_property -dict {PACKAGE_PIN AH10 } [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports rx_sync0_p] ; ## H13 FMC_HPC_LA07_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports rx_sync0_n] ; ## H14 FMC_HPC_LA07_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync1_p] ; ## H10 FMC_HPC_LA04_P
|
||||||
|
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync1_n] ; ## H11 FMC_HPC_LA04_N
|
||||||
|
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## G02 FMC_HPC_CLK1_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## G03 FMC_HPC_CLK1_M2C_N
|
||||||
|
|
||||||
|
# ADC control lines
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_pdwn] ; ## H08 FMC_HPC_LA02_N
|
||||||
|
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## G09 FMC_HPC_LA03_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## G10 FMC_HPC_LA03_N
|
||||||
|
|
||||||
|
# SPI interfaces
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_adc_csn] ; ## C10 FMC_HPC_LA06_P
|
||||||
|
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports spi_adc_clk] ; ## G36 FMC_HPC_LA33_P
|
||||||
|
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_adc_miso] ; ## H07 FMC_HPC_LA02_P
|
||||||
|
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports spi_adc_mosi] ; ## G37 FMC_HPC_LA33_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports spi_vco_csn] ; ## H19 FMC_HPC_LA15_P
|
||||||
|
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports spi_vco_clk] ; ## H16 FMC_HPC_LA11_P
|
||||||
|
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports spi_vco_mosi] ; ## H17 FMC_HPC_LA11_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_csn] ; ## H25 FMC_HPC_LA21_P
|
||||||
|
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_clk] ; ## H22 FMC_HPC_LA19_P
|
||||||
|
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_miso] ; ## H26 FMC_HPC_LA21_N
|
||||||
|
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_mosi] ; ## H23 FMC_HPC_LA19_N
|
||||||
|
|
||||||
|
# Laser driver and GPIOs
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports laser_driver_p] ; ## C22 FMC_HPC_LA18_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports laser_driver_n] ; ## C23 FMC_HPC_LA18_CC_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports laser_driver_en_n] ; ## C26 FMC_HPC_LA27_P
|
||||||
|
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports laser_driver_otw_n] ; ## C27 FMC_HPC_LA27_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports laser_gpio[0]] ; ## D20 FMC_HPC_LA17_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports laser_gpio[1]] ; ## D21 FMC_HPC_LA17_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports laser_gpio[2]] ; ## D23 FMC_HPC_LA23_P
|
||||||
|
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports laser_gpio[3]] ; ## D24 FMC_HPC_LA23_N
|
||||||
|
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports laser_gpio[4]] ; ## D26 FMC_HPC_LA26_P
|
||||||
|
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports laser_gpio[5]] ; ## D27 FMC_HPC_LA26_N
|
||||||
|
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports laser_gpio[6]] ; ## G24 FMC_HPC_LA22_P
|
||||||
|
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports laser_gpio[7]] ; ## G25 FMC_HPC_LA22_N
|
||||||
|
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[8]] ; ## G27 FMC_HPC_LA25_P
|
||||||
|
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[9]] ; ## G28 FMC_HPC_LA25_N
|
||||||
|
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports laser_gpio[10]] ; ## G30 FMC_HPC_LA29_P
|
||||||
|
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports laser_gpio[11]] ; ## G31 FMC_HPC_LA29_N
|
||||||
|
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[12]] ; ## G33 FMC_HPC_LA31_P
|
||||||
|
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[13]] ; ## G34 FMC_HPC_LA31_N
|
||||||
|
|
||||||
|
# AFE vref selection
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports afe_sel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N
|
||||||
|
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports afe_sel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports afe_sel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports afe_sel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P
|
||||||
|
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports afe_sel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N
|
||||||
|
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports afe_sel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P
|
||||||
|
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports afe_sel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N
|
||||||
|
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports afe_sel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P
|
||||||
|
|
||||||
|
# AFE DAC I2C and control
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports afe_dac_sda] ; ## D15 FMC_HPC_LA09_N
|
||||||
|
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_dac_scl] ; ## D17 FMC_HPC_LA13_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports afe_dac_load] ; ## G06 FMC_HPC_LA00_CC_P
|
||||||
|
|
||||||
|
# AFE ADC SPI and control
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports afe_adc_sclk] ; ## G07 FMC_HPC_LA00_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports afe_adc_scn] ; ## G12 FMC_HPC_LA08_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports afe_adc_convst] ; ## G13 FMC_HPC_LA08_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports afe_adc_sdo] ; ## G15 FMC_HPC_LA12_P
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
create_clock -name rx_device_clk -period 4.00 [get_ports rx_device_clk_p]
|
||||||
|
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
|
||||||
|
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9694_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||||
|
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
source ../../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||||
|
|
||||||
|
adi_project ad_fmclidar1_ebz_zc706
|
||||||
|
adi_project_files ad_fmclidar1_ebz_zc706 [list \
|
||||||
|
"system_top.v" \
|
||||||
|
"system_constr.xdc"\
|
||||||
|
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||||
|
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||||
|
|
||||||
|
adi_project_run ad_fmclidar1_ebz_zc706
|
||||||
|
|
@ -0,0 +1,298 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
// developed independently, and may be accompanied by separate and unique license
|
||||||
|
// terms.
|
||||||
|
//
|
||||||
|
// The user should read each of these license terms, and understand the
|
||||||
|
// freedoms and responsibilities that he or she has by using this source/core.
|
||||||
|
//
|
||||||
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE.
|
||||||
|
//
|
||||||
|
// Redistribution and use of source or resulting binaries, with or without modification
|
||||||
|
// of this file, are permitted under one of the following two license terms:
|
||||||
|
//
|
||||||
|
// 1. The GNU General Public License version 2 as published by the
|
||||||
|
// Free Software Foundation, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_GPL2), and also online at:
|
||||||
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||||
|
//
|
||||||
|
// OR
|
||||||
|
//
|
||||||
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||||
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||||
|
// This will allow to generate bit files and not release the source code,
|
||||||
|
// as long as it attaches to an ADI device.
|
||||||
|
//
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
inout [14:0] ddr_addr,
|
||||||
|
inout [ 2:0] ddr_ba,
|
||||||
|
inout ddr_cas_n,
|
||||||
|
inout ddr_ck_n,
|
||||||
|
inout ddr_ck_p,
|
||||||
|
inout ddr_cke,
|
||||||
|
inout ddr_cs_n,
|
||||||
|
inout [ 3:0] ddr_dm,
|
||||||
|
inout [31:0] ddr_dq,
|
||||||
|
inout [ 3:0] ddr_dqs_n,
|
||||||
|
inout [ 3:0] ddr_dqs_p,
|
||||||
|
inout ddr_odt,
|
||||||
|
inout ddr_ras_n,
|
||||||
|
inout ddr_reset_n,
|
||||||
|
inout ddr_we_n,
|
||||||
|
|
||||||
|
inout fixed_io_ddr_vrn,
|
||||||
|
inout fixed_io_ddr_vrp,
|
||||||
|
inout [53:0] fixed_io_mio,
|
||||||
|
inout fixed_io_ps_clk,
|
||||||
|
inout fixed_io_ps_porb,
|
||||||
|
inout fixed_io_ps_srstb,
|
||||||
|
|
||||||
|
inout [14:0] gpio_bd,
|
||||||
|
|
||||||
|
output hdmi_out_clk,
|
||||||
|
output hdmi_vsync,
|
||||||
|
output hdmi_hsync,
|
||||||
|
output hdmi_data_e,
|
||||||
|
output [23:0] hdmi_data,
|
||||||
|
|
||||||
|
output spdif,
|
||||||
|
|
||||||
|
inout iic_scl,
|
||||||
|
inout iic_sda,
|
||||||
|
|
||||||
|
input rx_ref_clk_p,
|
||||||
|
input rx_ref_clk_n,
|
||||||
|
input rx_device_clk_p,
|
||||||
|
input rx_device_clk_n,
|
||||||
|
output rx_sync0_p,
|
||||||
|
output rx_sync0_n,
|
||||||
|
output rx_sync1_p,
|
||||||
|
output rx_sync1_n,
|
||||||
|
input rx_sysref_p,
|
||||||
|
input rx_sysref_n,
|
||||||
|
input [ 3:0] rx_data_p,
|
||||||
|
input [ 3:0] rx_data_n,
|
||||||
|
|
||||||
|
inout adc_fdb,
|
||||||
|
inout adc_fda,
|
||||||
|
inout adc_pdwn,
|
||||||
|
|
||||||
|
// DAQ board's ADC SPI
|
||||||
|
|
||||||
|
output spi_adc_csn,
|
||||||
|
output spi_adc_clk,
|
||||||
|
output spi_adc_mosi,
|
||||||
|
input spi_adc_miso,
|
||||||
|
|
||||||
|
// DAQ board's clock chip
|
||||||
|
|
||||||
|
output spi_clkgen_csn,
|
||||||
|
output spi_clkgen_clk,
|
||||||
|
output spi_clkgen_mosi,
|
||||||
|
input spi_clkgen_miso,
|
||||||
|
|
||||||
|
// DAQ board's vco chip
|
||||||
|
|
||||||
|
output spi_vco_csn,
|
||||||
|
output spi_vco_clk,
|
||||||
|
output spi_vco_mosi,
|
||||||
|
|
||||||
|
// AFE board's DAC
|
||||||
|
|
||||||
|
inout afe_dac_sda,
|
||||||
|
inout afe_dac_scl,
|
||||||
|
output afe_dac_clr_n,
|
||||||
|
output afe_dac_load,
|
||||||
|
|
||||||
|
// AFE board's ADC
|
||||||
|
|
||||||
|
output afe_adc_sclk,
|
||||||
|
output afe_adc_scn,
|
||||||
|
output afe_adc_sdo,
|
||||||
|
output afe_adc_convst,
|
||||||
|
|
||||||
|
// Laser driver differential line
|
||||||
|
|
||||||
|
output laser_driver_p,
|
||||||
|
output laser_driver_n,
|
||||||
|
|
||||||
|
output laser_driver_en_n,
|
||||||
|
input laser_driver_otw_n,
|
||||||
|
|
||||||
|
// GPIO's for the laser board
|
||||||
|
|
||||||
|
inout [13:0] laser_gpio,
|
||||||
|
|
||||||
|
// Vref selects for AFE board
|
||||||
|
|
||||||
|
output [ 7:0] afe_sel
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire [63:0] gpio_i;
|
||||||
|
wire [63:0] gpio_o;
|
||||||
|
wire [63:0] gpio_t;
|
||||||
|
wire rx_ref_clk;
|
||||||
|
wire rx_sync;
|
||||||
|
wire rx_sysref;
|
||||||
|
wire rx_device_clk;
|
||||||
|
wire laser_driver;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (rx_ref_clk_p),
|
||||||
|
.IB (rx_ref_clk_n),
|
||||||
|
.O (rx_ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync0 (
|
||||||
|
.I (rx_sync),
|
||||||
|
.O (rx_sync0_p),
|
||||||
|
.OB (rx_sync0_n));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync1 (
|
||||||
|
.I (rx_sync),
|
||||||
|
.O (rx_sync1_p),
|
||||||
|
.OB (rx_sync1_n));
|
||||||
|
|
||||||
|
IBUFGDS i_rx_device_clk (
|
||||||
|
.I (rx_device_clk_p),
|
||||||
|
.IB (rx_device_clk_n),
|
||||||
|
.O (rx_device_clk));
|
||||||
|
|
||||||
|
IBUFDS i_rx_sysref (
|
||||||
|
.I (rx_sysref_p),
|
||||||
|
.IB (rx_sysref_n),
|
||||||
|
.O (rx_sysref));
|
||||||
|
|
||||||
|
// laser driver
|
||||||
|
|
||||||
|
OBUFDS i_obufds_laser_driver (
|
||||||
|
.I (laser_driver),
|
||||||
|
.O (laser_driver_p),
|
||||||
|
.OB (laser_driver_n));
|
||||||
|
|
||||||
|
// GPIO connections to the FMC connector
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(28)) i_fmc_iobuf (
|
||||||
|
.dio_t ({8'b0, gpio_t[51:38], 3'b0, gpio_t[34:32]}),
|
||||||
|
.dio_i ({gpio_o[59:32]}),
|
||||||
|
.dio_o ({gpio_i[59:32]}),
|
||||||
|
.dio_p ({
|
||||||
|
afe_sel, // 59:52 - output only
|
||||||
|
laser_gpio, // 51:38
|
||||||
|
afe_adc_convst, // 37 - output only
|
||||||
|
afe_dac_load, // 36 - output only
|
||||||
|
afe_dac_clr_n, // 35 - output only
|
||||||
|
adc_pdwn, // 34
|
||||||
|
adc_fdb, // 33
|
||||||
|
adc_fda // 32
|
||||||
|
}));
|
||||||
|
|
||||||
|
// GPIO connections for the carrier
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
|
||||||
|
.dio_t (gpio_t[14:0]),
|
||||||
|
.dio_i (gpio_o[14:0]),
|
||||||
|
.dio_o (gpio_i[14:0]),
|
||||||
|
.dio_p (gpio_bd));
|
||||||
|
|
||||||
|
// block design instance
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr_addr (ddr_addr),
|
||||||
|
.ddr_ba (ddr_ba),
|
||||||
|
.ddr_cas_n (ddr_cas_n),
|
||||||
|
.ddr_ck_n (ddr_ck_n),
|
||||||
|
.ddr_ck_p (ddr_ck_p),
|
||||||
|
.ddr_cke (ddr_cke),
|
||||||
|
.ddr_cs_n (ddr_cs_n),
|
||||||
|
.ddr_dm (ddr_dm),
|
||||||
|
.ddr_dq (ddr_dq),
|
||||||
|
.ddr_dqs_n (ddr_dqs_n),
|
||||||
|
.ddr_dqs_p (ddr_dqs_p),
|
||||||
|
.ddr_odt (ddr_odt),
|
||||||
|
.ddr_ras_n (ddr_ras_n),
|
||||||
|
.ddr_reset_n (ddr_reset_n),
|
||||||
|
.ddr_we_n (ddr_we_n),
|
||||||
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||||
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||||
|
.fixed_io_mio (fixed_io_mio),
|
||||||
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||||
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||||
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||||
|
.gpio_i (gpio_i),
|
||||||
|
.gpio_o (gpio_o),
|
||||||
|
.gpio_t (gpio_t),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.rx_data_0_n (rx_data_n[0]),
|
||||||
|
.rx_data_0_p (rx_data_p[0]),
|
||||||
|
.rx_data_1_n (rx_data_n[1]),
|
||||||
|
.rx_data_1_p (rx_data_p[1]),
|
||||||
|
.rx_data_2_n (rx_data_n[2]),
|
||||||
|
.rx_data_2_p (rx_data_p[2]),
|
||||||
|
.rx_data_3_n (rx_data_n[3]),
|
||||||
|
.rx_data_3_p (rx_data_p[3]),
|
||||||
|
.rx_ref_clk (rx_ref_clk),
|
||||||
|
.rx_device_clk (rx_device_clk),
|
||||||
|
.rx_sync_0 (rx_sync),
|
||||||
|
.rx_sysref_0 (rx_sysref),
|
||||||
|
.spdif (spdif),
|
||||||
|
.laser_driver (laser_driver),
|
||||||
|
.laser_driver_en_n (laser_driver_en_n),
|
||||||
|
.laser_driver_otw_n (laser_driver_otw_n),
|
||||||
|
.iic_dac_scl_io (afe_dac_scl),
|
||||||
|
.iic_dac_sda_io (afe_dac_sda),
|
||||||
|
.spi0_clk_i (spi_adc_clk),
|
||||||
|
.spi0_clk_o (spi_adc_clk),
|
||||||
|
.spi0_csn_0_o (spi_adc_csn),
|
||||||
|
.spi0_csn_i (1'b1),
|
||||||
|
.spi0_sdi_i (spi_adc_miso),
|
||||||
|
.spi0_sdo_i (spi_adc_mosi),
|
||||||
|
.spi0_sdo_o (spi_adc_mosi),
|
||||||
|
.spi1_clk_i (spi_clkgen_clk),
|
||||||
|
.spi1_clk_o (spi_clkgen_clk),
|
||||||
|
.spi1_csn_0_o (spi_clkgen_csn),
|
||||||
|
.spi1_csn_i (1'b1),
|
||||||
|
.spi1_sdi_i (spi_clkgen_miso),
|
||||||
|
.spi1_sdo_i (spi_clkgen_mosi),
|
||||||
|
.spi1_sdo_o (spi_clkgen_mosi),
|
||||||
|
.spi_vco_csn_i (1'b1),
|
||||||
|
.spi_vco_csn_o (spi_vco_csn),
|
||||||
|
.spi_vco_clk_i (1'b0),
|
||||||
|
.spi_vco_clk_o (spi_vco_clk),
|
||||||
|
.spi_vco_sdo_i (1'b0),
|
||||||
|
.spi_vco_sdo_o (spi_vco_mosi),
|
||||||
|
.spi_vco_sdi_i (1'b0),
|
||||||
|
.spi_afe_adc_csn_i (1'b1),
|
||||||
|
.spi_afe_adc_csn_o (afe_adc_scn),
|
||||||
|
.spi_afe_adc_clk_i (1'b0),
|
||||||
|
.spi_afe_adc_clk_o (afe_adc_sclk),
|
||||||
|
.spi_afe_adc_sdo_i (1'b0),
|
||||||
|
.spi_afe_adc_sdo_o (afe_adc_sdo),
|
||||||
|
.spi_afe_adc_sdi_i (1'b0));
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
Reference in New Issue