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Revert "Move GTM projects to gtm_projects branch" 

This reverts commit 171093eca4.
main
Istvan Csomortani 2019-03-21 06:24:45 +00:00 committed by István Csomortáni
parent f22f448d4b
commit 21ce53f765
59 changed files with 4318 additions and 0 deletions
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6
projects/ad5766_sdz/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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projects/ad5766_sdz/common/ad5766_bd.tcl Normal file
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# create a SPI Engine architecture
create_bd_cell -type hier spi
current_bd_instance /spi
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir O irq
create_bd_pin -dir O dma_clk
create_bd_pin -dir I dma_enable
create_bd_pin -dir O dma_valid
create_bd_pin -dir I -from 15 -to 0 dma_data
create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir I dma_underflow
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
ad_ip_instance spi_engine_execution execution
ad_ip_instance axi_spi_engine axi
ad_ip_instance axi_ad5766 axi_ad5766
ad_ip_instance spi_engine_interconnect interconnect
ad_ip_parameter execution CONFIG.NUM_OF_CS 1
ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
ad_ip_parameter interconnect CONFIG.NUM_OF_SDI 2
ad_connect axi/spi_engine_offload_ctrl0 axi_ad5766/spi_engine_offload_ctrl
ad_connect axi/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi_ad5766/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
ad_connect m_spi execution/spi
ad_connect dma_data axi_ad5766/dma_data
ad_connect dma_enable axi_ad5766/dma_enable
ad_connect dma_valid axi_ad5766/dma_valid
ad_connect dma_xfer_req axi_ad5766/dma_xfer_req
ad_connect dma_underflow axi_ad5766/dma_underflow
ad_connect clk execution/clk
ad_connect clk axi/s_axi_aclk
ad_connect clk axi_ad5766/s_axi_aclk
ad_connect clk axi_ad5766/spi_clk
ad_connect clk axi_ad5766/ctrl_clk
ad_connect clk axi/spi_clk
ad_connect clk interconnect/clk
ad_connect dma_clk axi_ad5766/dma_clk
ad_connect axi/spi_resetn axi_ad5766/spi_resetn
ad_connect axi/spi_resetn execution/resetn
ad_connect axi/spi_resetn interconnect/resetn
ad_connect resetn axi/s_axi_aresetn
ad_connect resetn axi_ad5766/s_axi_aresetn
ad_connect irq axi/irq
current_bd_instance /
ad_connect sys_cpu_clk spi/clk
ad_connect sys_cpu_resetn spi/resetn
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
ad_connect spi/m_spi spi
ad_ip_instance axi_dmac axi_ad5766_dac_dma
ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_TYPE_DEST 2
ad_ip_parameter axi_ad5766_dac_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad5766_dac_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad5766_dac_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad5766_dac_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad5766_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 16
ad_connect spi/dma_clk axi_ad5766_dac_dma/fifo_rd_clk
ad_connect spi/dma_valid axi_ad5766_dac_dma/fifo_rd_en
ad_connect spi/dma_xfer_req axi_ad5766_dac_dma/fifo_rd_xfer_req
ad_connect spi/dma_data axi_ad5766_dac_dma/fifo_rd_dout
ad_connect spi/dma_underflow axi_ad5766_dac_dma/fifo_rd_underflow
ad_connect spi/dma_enable VCC
ad_cpu_interconnect 0x44a00000 spi/axi
ad_cpu_interconnect 0x44a10000 spi/axi_ad5766
ad_cpu_interconnect 0x44a20000 axi_ad5766_dac_dma
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad5766_dac_dma/m_src_axi
ad_connect sys_cpu_resetn axi_ad5766_dac_dma/m_src_axi_aresetn
ad_cpu_interrupt ps-12 mb-13 spi/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad5766_dac_dma/irq

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad5766_sdz_zed
M_DEPS += ../common/ad5766_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_ad5766
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += util_i2c_mixer
include ../../scripts/project-xilinx.mk

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projects/ad5766_sdz/zed/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad5766_bd.tcl

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# SPI interface
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports spi_sdi] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA15_P
# reset signal
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports reset] ; ## FMC_LPC_LA21_P

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projects/ad5766_sdz/zed/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx ad5766_sdz_zed
adi_project_files ad5766_sdz_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run ad5766_sdz_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
input spi_sdi,
output spi_sdo,
output spi_sclk,
output spi_cs,
inout reset);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_reset (
.dio_t(gpio_t[32]),
.dio_i(gpio_o[32]),
.dio_o(gpio_i[32]),
.dio_p(reset));
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
assign gpio_i[63:33] = gpio_o[63:33];
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spi_sdo (spi_sdo),
.spi_sdo_t (),
.spi_sdi (spi_sdi),
.spi_cs (spi_cs),
.spi_sclk (spi_sclk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di
create_bd_port -dir I ad713x_odr
create_bd_port -dir O ad713x_sdpclk
# create a SPI Engine architecture for the parallel data interface of AD713x
# this design supports AD7132/AD7134/AD7136
create_bd_cell -type hier dual_ad7134
current_bd_instance /dual_ad7134
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir I odr
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
ad_ip_instance spi_engine_execution execution
ad_ip_parameter execution CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter execution CONFIG.NUM_OF_CS 1
ad_ip_parameter execution CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_instance axi_spi_engine axi
ad_ip_parameter axi CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
ad_ip_instance spi_engine_offload offload
ad_ip_parameter offload CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
ad_ip_instance spi_engine_interconnect interconnect
ad_ip_parameter interconnect CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $adc_num_of_channels
if {$adc_resolution == 24} {
ad_ip_instance util_axis_upscale axis_upscaler
ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS $adc_num_of_channels
ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH 24
ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
ad_connect axis_upscaler/dfmt_enable GND
ad_connect axis_upscaler/dfmt_type GND
ad_connect axis_upscaler/dfmt_se GND
}
ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
if {$adc_resolution == 24} {
ad_connect offload/offload_sdi axis_upscaler/s_axis
ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
ad_connect clk axis_upscaler/clk
ad_connect axi/spi_resetn axis_upscaler/resetn
} else {
ad_connect offload/offload_sdi M_AXIS_SAMPLE
}
ad_connect execution/spi m_spi
ad_connect clk offload/spi_clk
ad_connect clk offload/ctrl_clk
ad_connect clk execution/clk
ad_connect clk axi/s_axi_aclk
ad_connect clk axi/spi_clk
ad_connect clk interconnect/clk
ad_connect axi/spi_resetn offload/spi_resetn
ad_connect axi/spi_resetn execution/resetn
ad_connect axi/spi_resetn interconnect/resetn
ad_connect odr offload/trigger
ad_connect resetn axi/s_axi_aresetn
ad_connect irq axi/irq
current_bd_instance /
# dma to receive data stream
ad_ip_instance axi_dmac axi_ad7134_dma
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7134_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0
if {$adc_resolution == 24} {
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32 * $adc_num_of_channels]
} else {
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $adc_resolution * $adc_num_of_channels]
}
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128
# sdpclk clock generator - default clk0_out is 50 MHz
ad_ip_instance axi_clkgen axi_sdp_clkgen
ad_ip_parameter axi_sdp_clkgen CONFIG.CLKIN_PERIOD 10
ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_MUL 12
ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_DIV 2
ad_ip_parameter axi_sdp_clkgen CONFIG.CLK0_DIV 12
ad_connect sys_cpu_clk dual_ad7134/clk
ad_connect sys_cpu_clk axi_ad7134_dma/s_axis_aclk
ad_connect sys_cpu_clk axi_sdp_clkgen/clk
ad_connect sys_cpu_resetn dual_ad7134/resetn
ad_connect sys_cpu_resetn axi_ad7134_dma/m_dest_axi_aresetn
ad_connect dual_ad7134/m_spi ad713x_di
ad_connect dual_ad7134/odr ad713x_odr
ad_connect axi_ad7134_dma/s_axis dual_ad7134/M_AXIS_SAMPLE
ad_connect ad713x_sdpclk axi_sdp_clkgen/clk_0
ad_cpu_interconnect 0x44a00000 dual_ad7134/axi
ad_cpu_interconnect 0x44a30000 axi_ad7134_dma
ad_cpu_interconnect 0x44a40000 axi_sdp_clkgen
ad_cpu_interrupt "ps-13" "mb-13" axi_ad7134_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" dual_ad7134/irq
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad7134_dma/m_dest_axi

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7134_fmc_zed
M_DEPS += ../common/ad7134_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += util_axis_upscale
LIB_DEPS += util_i2c_mixer
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
# specify ADC resolution -- the design supports 16/24/32 bit resolutions
set adc_resolution 24
# ADC number of channels
set adc_num_of_channels 8
source ../common/ad7134_bd.tcl

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# ad713x SPI configuration interface
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdo] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sclk] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_cs[0]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_cs[1]] ; ## FMC_LPC_LA05_N
# ad713x data interface
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad713x_dclk] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad713x_din[0]] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports ad713x_din[1]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad713x_din[2]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad713x_din[3]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad713x_din[4]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ad713x_din[5]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports ad713x_din[6]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports ad713x_din[7]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad713x_odr] ; ## FMC_LPC_LA00_CC_P
# ad713x GPIO lines
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports ad713x_resetn[0]] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports ad713x_resetn[1]] ; ## FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad713x_pdn[0]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports ad713x_pdn[1]] ; ## FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad713x_mode[0]] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad713x_mode[1]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[0]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[1]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[2]] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[3]] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[4]] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[5]] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[6]] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports ad713x_gpio[7]] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkio[0]] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkio[1]] ; ## FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad713x_pinbspi] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports ad713x_dclkmode] ; ## FMC_LPC_LA14_N
# ad713x reference clock (not used by default)
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad713x_sdpclk] ; ## FMC_LPC_LA01_CC_N

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx ad7134_fmc_zed
adi_project_files ad7134_fmc_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run ad7134_fmc_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
// ad713x SPI configuration interface
input ad713x_spi_sdi,
output ad713x_spi_sdo,
output ad713x_spi_sclk,
output [ 1:0] ad713x_spi_cs,
// ad713x data interface
output ad713x_dclk,
input [ 7:0] ad713x_din,
input ad713x_odr,
// ad713x GPIO lines
inout [ 1:0] ad713x_resetn,
inout [ 1:0] ad713x_pdn,
inout [ 1:0] ad713x_mode,
inout [ 7:0] ad713x_gpio,
inout [ 1:0] ad713x_dclkio,
inout ad713x_pinbspi,
inout ad713x_dclkmode,
// ad713x reference clock (not used by default)
output ad713x_sdpclk);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
assign gpio_i[63:50] = gpio_o[63:50];
ad_iobuf #(
.DATA_WIDTH(18)
) i_iobuf_ad713x_gpio (
.dio_t(gpio_t[49:32]),
.dio_i(gpio_o[49:32]),
.dio_o(gpio_i[49:32]),
.dio_p({ad713x_dclkmode, // [49]
ad713x_pinbspi, // [48]
ad713x_dclkio, // [47:46]
ad713x_gpio, // [45:38]
ad713x_mode, // [37:36]
ad713x_pdn, // [35:34]
ad713x_resetn})); // [33:32]
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spi0_clk_i (ad713x_spi_sclk),
.spi0_clk_o (ad713x_spi_sclk),
.spi0_csn_0_o (ad713x_spi_cs[0]),
.spi0_csn_1_o (ad713x_spi_cs[1]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (ad713x_spi_sdi),
.spi0_sdo_i (ad713x_spi_sdo),
.spi0_sdo_o (ad713x_spi_sdo),
.ad713x_di_sdo (),
.ad713x_di_sdo_t (),
.ad713x_di_sdi (ad713x_din[0]),
.ad713x_di_sdi_1 (ad713x_din[1]),
.ad713x_di_sdi_2 (ad713x_din[2]),
.ad713x_di_sdi_3 (ad713x_din[3]),
.ad713x_di_sdi_4 (ad713x_din[4]),
.ad713x_di_sdi_5 (ad713x_din[5]),
.ad713x_di_sdi_6 (ad713x_din[6]),
.ad713x_di_sdi_7 (ad713x_din[7]),
.ad713x_di_cs (),
.ad713x_di_sclk (ad713x_dclk),
.ad713x_odr (ad713x_odr),
.ad713x_sdpclk (ad713x_sdpclk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
# create a SPI Engine architecture
create_bd_cell -type hier spi
current_bd_instance /spi
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
ad_ip_instance spi_engine_execution execution
ad_ip_parameter execution CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter execution CONFIG.NUM_OF_CS 1
ad_ip_parameter execution CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_instance axi_spi_engine axi
ad_ip_parameter axi CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
ad_ip_instance spi_engine_offload offload
ad_ip_parameter offload CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_instance spi_engine_interconnect interconnect
ad_ip_parameter interconnect CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $adc_num_of_channels
ad_ip_instance util_pulse_gen trigger_gen
## to setup the sample rate of the system change the PULSE_PERIOD value
## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
## fsys_cpu_clk is defined to 100 MHZ
set cycle_per_sec_100mhz 100000000
set sampling_cycle [expr int(ceil(double($cycle_per_sec_100mhz) / $adc_sampling_rate))]
ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle
ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1
if {$adc_resolution < 16} {
ad_ip_instance util_axis_upscale axis_upscaler
ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS $adc_num_of_channels
ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH $adc_resolution
ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 16
ad_connect clk axis_upscaler/clk
ad_connect axi/spi_resetn axis_upscaler/resetn
ad_connect offload/offload_sdi axis_upscaler/s_axis
ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
ad_connect axis_upscaler/dfmt_enable GND
ad_connect axis_upscaler/dfmt_type GND
ad_connect axis_upscaler/dfmt_se GND
} else {
ad_connect offload/offload_sdi M_AXIS_SAMPLE
}
ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
ad_connect execution/spi m_spi
ad_connect clk offload/spi_clk
ad_connect clk offload/ctrl_clk
ad_connect clk execution/clk
ad_connect clk axi/s_axi_aclk
ad_connect clk axi/spi_clk
ad_connect clk interconnect/clk
ad_connect clk trigger_gen/clk
ad_connect axi/spi_resetn offload/spi_resetn
ad_connect axi/spi_resetn execution/resetn
ad_connect axi/spi_resetn interconnect/resetn
ad_connect axi/spi_resetn trigger_gen/rstn
ad_connect trigger_gen/pulse_period_en GND
ad_connect trigger_gen/pulse_period GND
ad_connect trigger_gen/pulse offload/trigger
ad_connect resetn axi/s_axi_aresetn
ad_connect irq axi/irq
current_bd_instance /
ad_ip_instance axi_dmac axi_ad738x_dma
ad_ip_parameter axi_ad738x_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad738x_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad738x_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad738x_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad738x_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $adc_num_of_channels * 16]
ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect sys_cpu_clk spi/clk
ad_connect sys_cpu_resetn spi/resetn
ad_connect sys_cpu_resetn axi_ad738x_dma/m_dest_axi_aresetn
ad_connect spi/m_spi spi
ad_connect axi_ad738x_dma/s_axis spi/M_AXIS_SAMPLE
ad_cpu_interconnect 0x44a00000 spi/axi
ad_cpu_interconnect 0x44a30000 axi_ad738x_dma
ad_connect sys_cpu_clk axi_ad738x_dma/s_axis_aclk
ad_cpu_interrupt "ps-13" "mb-13" axi_ad738x_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" spi/irq
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad738x_dma/m_dest_axi

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad738x_fmc_zed
M_DEPS += ../common/ad738x_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += util_axis_upscale
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pulse_gen
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
# specify ADC resolution -- the design supports 16/14/12 bit resolutions
set adc_resolution 16
# specify the number of active channel -- 1 or 2 or 4
set adc_num_of_channels 2
# specify ADC sampling rate in sample/seconds -- default is 3 MSPS
set adc_sampling_rate 3000000
source ../common/ad738x_bd.tcl

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# SPI interface
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_sdia] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdib] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA00_CC_N

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx ad738x_fmc_zed
adi_project_files ad738x_fmc_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run ad738x_fmc_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
input spi_sdia,
input spi_sdib,
output spi_sdo,
output spi_sclk,
output spi_cs);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
assign gpio_i[63:32] = gpio_o[63:32];
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spi_sdo (spi_sdo),
.spi_sdo_t (),
.spi_sdi (spi_sdia),
.spi_sdi_1 (spi_sdib),
.spi_cs (spi_cs),
.spi_sclk (spi_sclk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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global ad7616_if
# data interfaces
create_bd_port -dir O rx_sclk
create_bd_port -dir O rx_sdo
create_bd_port -dir I rx_sdi_0
create_bd_port -dir I rx_sdi_1
create_bd_port -dir O -from 15 -to 0 rx_db_o
create_bd_port -dir I -from 15 -to 0 rx_db_i
create_bd_port -dir O rx_db_t
create_bd_port -dir O rx_rd_n
create_bd_port -dir O rx_wr_n
# control lines
create_bd_port -dir O rx_cnvst
create_bd_port -dir O rx_cs_n
create_bd_port -dir I rx_busy
# instantiation
ad_ip_instance axi_ad7616 axi_ad7616
ad_ip_parameter axi_ad7616 CONFIG.IF_TYPE $ad7616_if
ad_ip_instance axi_dmac axi_ad7616_dma
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7616_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# interface connections
if {$ad7616_if == 0} {
ad_connect rx_sclk axi_ad7616/rx_sclk
ad_connect rx_sdo axi_ad7616/rx_sdo
ad_connect rx_sdi_0 axi_ad7616/rx_sdi_0
ad_connect rx_sdi_1 axi_ad7616/rx_sdi_1
ad_connect rx_cs_n axi_ad7616/rx_cs_n
ad_connect rx_cnvst axi_ad7616/rx_cnvst
ad_connect rx_busy axi_ad7616/rx_busy
} else {
ad_connect rx_db_o axi_ad7616/rx_db_o
ad_connect rx_db_i axi_ad7616/rx_db_i
ad_connect rx_db_t axi_ad7616/rx_db_t
ad_connect rx_rd_n axi_ad7616/rx_rd_n
ad_connect rx_wr_n axi_ad7616/rx_wr_n
ad_connect rx_cs_n axi_ad7616/rx_cs_n
ad_connect rx_cnvst axi_ad7616/rx_cnvst
ad_connect rx_busy axi_ad7616/rx_busy
}
ad_connect sys_cpu_clk axi_ad7616_dma/s_axi_aclk
ad_connect sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync
# interconnect
ad_cpu_interconnect 0x44A00000 axi_ad7616
ad_cpu_interconnect 0x44A30000 axi_ad7616_dma
# memory interconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad7616_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad7616_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad7616/irq

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7616_sdz_zc706
M_DEPS += serial_if_constr.xdc
M_DEPS += parallel_if_constr.xdc
M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_ad7616
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
include ../../scripts/project-xilinx.mk

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# ad7616
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

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# ad7616
# data interface
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi_0] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi_1] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad7616_bd.tcl

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
##--------------------------------------------------------------
# IMPORTANT: Set AD7616 operation and interface mode
#
# ad7616_if - Defines the interface type (serial OR parallel)
#
# LEGEND: Serial - 0
# Parallel - 1
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
#
##--------------------------------------------------------------
set ad7616_if 0
adi_project_xilinx ad7616_sdz_zc706
if { $ad7616_if == 0 } {
adi_project_files ad7616_sdz_zc706 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top_si.v" \
"serial_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
} elseif { $ad7616_if == 1 } {
adi_project_files ad7616_sdz_zc706 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top_pi.v" \
"parallel_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
} else {
return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
}
adi_project_run ad7616_sdz_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
inout [15:0] adc_db,
output adc_rd_n,
output adc_wr_n,
output adc_cs_n,
output adc_reset_n,
output adc_convst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;
// instantiations
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i (gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o (gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_seq_en, // 37
adc_chsel})); // 35:33
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.spdif (spdif),
.rx_cnvst (adc_convst),
.rx_cs_n (adc_cs_n),
.rx_busy (adc_busy),
.rx_db_o (adc_db_o),
.rx_db_i (adc_db_i),
.rx_db_t (adc_db_t),
.rx_rd_n (adc_rd_n),
.rx_wr_n (adc_wr_n)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
output spi_sclk,
output spi_sdo,
input spi_sdi_0,
input spi_sdi_1,
output spi_cs_n,
output adc_reset_n,
output adc_convst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel,
output adc_crcen,
output adc_burst,
output [ 2:0] adc_os);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_os, // 40:38
adc_seq_en, // 37
adc_burst, // 36
adc_chsel, // 35:33
adc_crcen})); // 32
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.spdif (spdif),
.rx_sclk (spi_sclk),
.rx_sdo (spi_sdo),
.rx_sdi_0 (spi_sdi_0),
.rx_sdi_1 (spi_sdi_1),
.rx_cnvst (adc_convst),
.rx_cs_n (spi_cs_n),
.rx_busy (adc_busy));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7616_sdz_zed
M_DEPS += serial_if_constr.xdc
M_DEPS += parallel_if_constr.xdc
M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_ad7616
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_i2c_mixer
include ../../scripts/project-xilinx.mk

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# ad7616
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N
# control lines
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

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# ad7616
# data interface
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports spi_sdi_0] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdi_1] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad7616_bd.tcl

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
##--------------------------------------------------------------
# IMPORTANT: Set AD7616 operation and interface mode
#
# ad7616_if - Defines the interface type (serial OR parallel)
#
# LEGEND: Serial - 0
# Parallel - 1
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
#
##--------------------------------------------------------------
set ad7616_if 0
adi_project_xilinx ad7616_sdz_zed
if { $ad7616_if == 0 } {
adi_project_files ad7616_sdz_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top_si.v" \
"serial_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
} elseif { $ad7616_if == 1 } {
adi_project_files ad7616_sdz_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top_pi.v" \
"parallel_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
} else {
return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
}
adi_project_run ad7616_sdz_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
inout [15:0] adc_db,
output adc_rd_n,
output adc_wr_n,
output adc_cs_n,
output adc_reset_n,
output adc_convst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;
// instantiations
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
.dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_seq_en, // 37
adc_chsel})); // 35:33
assign gpio_i[63:44] = gpio_o[63:44];
assign gpio_i[40:38] = gpio_o[40:38];
assign gpio_i[36] = gpio_o[36];
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.rx_cnvst (adc_convst),
.rx_cs_n (adc_cs_n),
.rx_busy (adc_busy),
.rx_db_o (adc_db_o),
.rx_db_i (adc_db_i),
.rx_db_t (adc_db_t),
.rx_rd_n (adc_rd_n),
.rx_wr_n (adc_wr_n)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
output spi_sclk,
output spi_sdo,
input spi_sdi_0,
input spi_sdi_1,
output spi_cs_n,
output adc_reset_n,
output adc_convst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel,
output adc_crcen,
output adc_burst,
output [ 2:0] adc_os);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_os, // 40:38
adc_seq_en, // 37
adc_burst, // 36
adc_chsel, // 35:33
adc_crcen})); // 32
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
assign gpio_i[63:44] = gpio_o[63:44];
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.rx_cnvst (adc_convst),
.rx_sclk (spi_sclk),
.rx_sdo (spi_sdo),
.rx_sdi_0 (spi_sdi_0),
.rx_sdi_1 (spi_sdi_1),
.rx_cs_n (spi_cs_n),
.rx_busy (adc_busy)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc1_spi
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc2_spi
create_bd_port -dir I adc1_data_ready
create_bd_port -dir I adc2_data_ready
# create a SPI Engine architecture for both ADCs
create_bd_cell -type hier spi_adc1
current_bd_instance /spi_adc1
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir I drdy
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
# DATA_WIDTH is set to 8, so the granularity of the transaction will be 8 bit
# So we can to support 16bit 24bit and 32bit transfers
ad_ip_instance spi_engine_execution execution
ad_ip_parameter execution CONFIG.DATA_WIDTH 8
ad_ip_parameter execution CONFIG.NUM_OF_CS 1
ad_ip_instance axi_spi_engine axi_1
ad_ip_parameter axi_1 CONFIG.DATA_WIDTH 8
ad_ip_parameter axi_1 CONFIG.NUM_OFFLOAD 1
ad_ip_instance spi_engine_offload offload
ad_ip_parameter offload CONFIG.DATA_WIDTH 8
ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
ad_ip_instance spi_engine_interconnect interconnect
ad_ip_parameter interconnect CONFIG.DATA_WIDTH 8
# to convert the 8bit AXI stream to 24bit AXI stream
ad_ip_instance axis_dwidth_converter m_axis_samples_24
ad_ip_parameter m_axis_samples_24 CONFIG.M_TDATA_NUM_BYTES 3
# upscale the data to 32bit, samples should be multiple of 16bit
ad_ip_instance util_axis_upscale axis_upscaler
ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS 1
ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH 24
ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
ad_connect axis_upscaler/dfmt_enable GND
ad_connect axis_upscaler/dfmt_type GND
ad_connect axis_upscaler/dfmt_se GND
ad_connect axi_1/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi_1/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
ad_connect offload/offload_sdi m_axis_samples_24/S_AXIS
ad_connect m_axis_samples_24/M_AXIS axis_upscaler/s_axis
ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
ad_connect execution/spi m_spi
ad_connect clk offload/spi_clk
ad_connect clk offload/ctrl_clk
ad_connect clk execution/clk
ad_connect clk axi_1/s_axi_aclk
ad_connect clk axi_1/spi_clk
ad_connect clk interconnect/clk
ad_connect clk m_axis_samples_24/aclk
ad_connect clk axis_upscaler/clk
ad_connect axi_1/spi_resetn offload/spi_resetn
ad_connect axi_1/spi_resetn execution/resetn
ad_connect axi_1/spi_resetn interconnect/resetn
ad_connect axi_1/spi_resetn m_axis_samples_24/aresetn
ad_connect axi_1/spi_resetn axis_upscaler/resetn
ad_connect drdy offload/trigger
ad_connect resetn axi_1/s_axi_aresetn
ad_connect irq axi_1/irq
current_bd_instance /
create_bd_cell -type hier spi_adc2
current_bd_instance /spi_adc2
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir I drdy
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
ad_ip_instance spi_engine_execution execution
ad_ip_parameter execution CONFIG.DATA_WIDTH 8
ad_ip_parameter execution CONFIG.NUM_OF_CS 1
ad_ip_instance axi_spi_engine axi_2
ad_ip_parameter axi_2 CONFIG.DATA_WIDTH 8
ad_ip_parameter axi_2 CONFIG.NUM_OFFLOAD 1
ad_ip_instance spi_engine_offload offload
ad_ip_parameter offload CONFIG.DATA_WIDTH 8
ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
ad_ip_instance spi_engine_interconnect interconnect
ad_ip_parameter interconnect CONFIG.DATA_WIDTH 8
# to convert the 8bit AXI stream to 24bit AXI stream
ad_ip_instance axis_dwidth_converter m_axis_samples_24
ad_ip_parameter m_axis_samples_24 CONFIG.M_TDATA_NUM_BYTES 3
# upscale the data to 32bit, samples should be multiple of 16bit
ad_ip_instance util_axis_upscale axis_upscaler
ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS 1
ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH 24
ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
ad_connect axis_upscaler/dfmt_enable GND
ad_connect axis_upscaler/dfmt_type GND
ad_connect axis_upscaler/dfmt_se GND
ad_connect axi_2/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi_2/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
ad_connect offload/offload_sdi m_axis_samples_24/S_AXIS
ad_connect m_axis_samples_24/M_AXIS axis_upscaler/s_axis
ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
ad_connect execution/spi m_spi
ad_connect clk offload/spi_clk
ad_connect clk offload/ctrl_clk
ad_connect clk execution/clk
ad_connect clk axi_2/s_axi_aclk
ad_connect clk axi_2/spi_clk
ad_connect clk interconnect/clk
ad_connect clk m_axis_samples_24/aclk
ad_connect clk axis_upscaler/clk
ad_connect axi_2/spi_resetn offload/spi_resetn
ad_connect axi_2/spi_resetn execution/resetn
ad_connect axi_2/spi_resetn interconnect/resetn
ad_connect axi_2/spi_resetn m_axis_samples_24/aresetn
ad_connect axi_2/spi_resetn axis_upscaler/resetn
ad_connect drdy offload/trigger
ad_connect resetn axi_2/s_axi_aresetn
ad_connect irq axi_2/irq
current_bd_instance /
ad_connect adc1_data_ready spi_adc1/drdy
ad_connect adc2_data_ready spi_adc2/drdy
# dma for the ADC1
ad_ip_instance axi_dmac axi_ad77681_dma_1
ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad77681_dma_1 CONFIG.CYCLIC 0
ad_ip_parameter axi_ad77681_dma_1 CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad77681_dma_1 CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad77681_dma_1 CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect sys_cpu_clk spi_adc1/clk
ad_connect sys_cpu_resetn spi_adc1/resetn
ad_connect sys_cpu_resetn axi_ad77681_dma_1/m_dest_axi_aresetn
ad_connect spi_adc1/m_spi adc1_spi
ad_connect axi_ad77681_dma_1/s_axis spi_adc1/M_AXIS_SAMPLE
# dma for the ADC2
ad_ip_instance axi_dmac axi_ad77681_dma_2
ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad77681_dma_2 CONFIG.CYCLIC 0
ad_ip_parameter axi_ad77681_dma_2 CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad77681_dma_2 CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad77681_dma_2 CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect sys_cpu_clk spi_adc2/clk
ad_connect sys_cpu_resetn spi_adc2/resetn
ad_connect sys_cpu_resetn axi_ad77681_dma_2/m_dest_axi_aresetn
ad_connect spi_adc2/m_spi adc2_spi
ad_connect axi_ad77681_dma_2/s_axis spi_adc2/M_AXIS_SAMPLE
# AXI address definitions
ad_cpu_interconnect 0x44a00000 spi_adc1/axi_1
ad_cpu_interconnect 0x44b00000 spi_adc2/axi_2
ad_cpu_interconnect 0x44a30000 axi_ad77681_dma_1
ad_cpu_interconnect 0x44b30000 axi_ad77681_dma_2
ad_connect sys_cpu_clk axi_ad77681_dma_1/s_axis_aclk
ad_connect sys_cpu_clk axi_ad77681_dma_2/s_axis_aclk
# interrupts
ad_cpu_interrupt "ps-13" "mb-13" axi_ad77681_dma_1/irq
ad_cpu_interrupt "ps-12" "mb-12" axi_ad77681_dma_2/irq
ad_cpu_interrupt "ps-11" "mb-11" spi_adc1/irq
ad_cpu_interrupt "ps-10" "mb-10" spi_adc2/irq
# memory interconnects
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad77681_dma_1/m_dest_axi
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad77681_dma_2/m_dest_axi

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad77681evb_zed
M_DEPS += ../common/ad77681evb_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/xilinx/common/ad_data_clk.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += util_axis_upscale
LIB_DEPS += util_i2c_mixer
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad77681evb_bd.tcl

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# SPI interface
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad7768_0_spi_sclk] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE PULLTYPE PULLUP} [get_ports ad7768_0_spi_miso] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad7768_0_spi_mosi] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad7768_0_spi_cs] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad7768_1_spi_sclk] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25 IOB TRUE PULLTYPE PULLUP} [get_ports ad7768_1_spi_miso] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad7768_1_spi_mosi] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad7768_1_spi_cs] ; ## FMC_LPC_LA04_N
# reset and GPIO signals
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports ad7768_0_reset] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports ad7768_0_gpio[0]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports ad7768_0_gpio[1]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports ad7768_0_gpio[2]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports ad7768_0_gpio[3]] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports ad7768_1_reset] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ad7768_1_gpio[0]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports ad7768_1_gpio[1]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports ad7768_1_gpio[2]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports ad7768_1_gpio[3]] ; ## FMC_LPC_LA11_N
# syncronization and timing
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad7768_0_drdy] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports ad7768_0_sync_out] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad7768_0_sync_in] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad7768_0_mclk] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad7768_1_drdy] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad7768_1_sync_out] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad7768_1_sync_in] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad7768_1_mclk] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad7768_mclk_return] ; ## FMC_LPC_LA00_CC_P

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projects/ad77681evb/zed/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx ad77681evb_zed
adi_project_files ad77681evb_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run ad77681evb_zed

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projects/ad77681evb/zed/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
inout ad7768_0_reset,
inout ad7768_0_sync_out,
inout ad7768_0_sync_in,
inout [ 3:0] ad7768_0_gpio,
inout ad7768_1_reset,
inout ad7768_1_sync_out,
inout ad7768_1_sync_in,
inout [ 3:0] ad7768_1_gpio,
input ad7768_0_mclk,
input ad7768_1_mclk,
output ad7768_mclk_return,
input ad7768_0_spi_miso,
output ad7768_0_spi_mosi,
output ad7768_0_spi_sclk,
output ad7768_0_spi_cs,
input ad7768_0_drdy,
input ad7768_1_spi_miso,
output ad7768_1_spi_mosi,
output ad7768_1_spi_sclk,
output ad7768_1_spi_cs,
input ad7768_1_drdy);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire ad7768_0_mclk_s;
wire ad7768_1_mclk_s;
// instantiations
ad_data_clk #(.SINGLE_ENDED (1)) i_ad7768_0_mclk_receiver(
.rst (1'b1),
.locked (),
.clk_in_p (ad7768_0_mclk),
.clk_in_n (1'd0),
.clk(ad7768_0_mclk_s));
ad_data_clk #(.SINGLE_ENDED (1)) i_ad7768_1_mclk_receiver(
.rst (1'b1),
.locked (),
.clk_in_p (ad7768_1_mclk),
.clk_in_n (1'd0),
.clk(ad7768_1_mclk_s));
assign ad7768_mclk_return = ad7768_0_mclk_s;
ad_iobuf #(
.DATA_WIDTH(7)
) i_iobuf_ad7768_1_gpio (
.dio_t(gpio_t[54:48]),
.dio_i(gpio_o[54:48]),
.dio_o(gpio_i[54:48]),
.dio_p({ad7768_1_gpio,
ad7768_1_sync_in,
ad7768_1_sync_out,
ad7768_1_reset}));
ad_iobuf #(
.DATA_WIDTH(7)
) i_iobuf_ad7768_0_gpio (
.dio_t(gpio_t[38:32]),
.dio_i(gpio_o[38:32]),
.dio_o(gpio_i[38:32]),
.dio_p({ad7768_0_gpio,
ad7768_0_sync_in,
ad7768_0_sync_out,
ad7768_0_reset}));
assign gpio_i[47:39] = gpio_o[47:39];
assign gpio_i[63:55] = gpio_o[63:55];
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
assign gpio_i[47:39] = gpio_o[47:39];
assign gpio_i[63:55] = gpio_o[63:55];
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.adc1_spi_sdo (ad7768_0_spi_mosi),
.adc1_spi_sdo_t (),
.adc1_spi_sdi (ad7768_0_spi_miso),
.adc1_spi_cs (ad7768_0_spi_cs),
.adc1_spi_sclk (ad7768_0_spi_sclk),
.adc1_data_ready (ad7768_0_drdy),
.adc2_spi_sdo (ad7768_1_spi_mosi),
.adc2_spi_sdo_t (),
.adc2_spi_sdi (ad7768_1_spi_miso),
.adc2_spi_cs (ad7768_1_spi_cs),
.adc2_spi_sclk (ad7768_1_spi_sclk),
.adc2_data_ready (ad7768_1_drdy));
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/ad7768evb/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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projects/ad7768evb/common/ad7768_if.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad7768_if (
// device-interface
input clk_in,
input ready_in,
input [ 7:0] data_in,
// data path interface
output adc_clk,
output reg adc_valid,
output reg [ 31:0] adc_data,
// control interface
input up_sshot,
input [ 1:0] up_format,
input up_crc_enable,
input up_crc_4_or_16_n,
input [ 35:0] up_status_clr,
output [ 35:0] up_status);
// internal registers
reg [ 1:0] adc_status_8 = 'd0;
reg [ 2:0] adc_status_7 = 'd0;
reg [ 2:0] adc_status_6 = 'd0;
reg [ 2:0] adc_status_5 = 'd0;
reg [ 2:0] adc_status_4 = 'd0;
reg [ 2:0] adc_status_3 = 'd0;
reg [ 2:0] adc_status_2 = 'd0;
reg [ 2:0] adc_status_1 = 'd0;
reg [ 2:0] adc_status_0 = 'd0;
reg [ 2:0] adc_seq = 'd0;
reg [ 4:0] adc_status = 'd0;
reg [ 63:0] adc_crc_8 = 'd0;
reg [ 7:0] adc_crc_mismatch_int = 'd0;
reg adc_crc_valid = 'd0;
reg [ 7:0] adc_crc_data = 'd0;
reg [ 7:0] adc_crc_mismatch_8 = 'd0;
reg adc_valid_int = 'd0;
reg [ 31:0] adc_data_int = 'd0;
reg [ 2:0] adc_seq_int = 'd0;
reg adc_enable_int = 'd0;
reg [ 3:0] adc_crc_scnt_int = 'd0;
reg [ 3:0] adc_crc_scnt_8 = 'd0;
reg [ 23:0] adc_seq_data = 'd0;
reg adc_seq_fmatch = 'd0;
reg [ 23:0] adc_seq_fdata = 'd0;
reg adc_seq_foos = 'd0;
reg [ 7:0] adc_enable_8 = 'd0;
reg [ 23:0] adc_seq_8 = 'd0;
reg adc_valid_8 = 'd0;
reg [ 31:0] adc_data_8 = 'd0;
reg [ 7:0] adc_ch_valid_d = 'd0;
reg [255:0] adc_ch_data_d0 = 'd0;
reg [255:0] adc_ch_data_d1 = 'd0;
reg [255:0] adc_ch_data_d2 = 'd0;
reg [255:0] adc_ch_data_d3 = 'd0;
reg [255:0] adc_ch_data_d4 = 'd0;
reg [255:0] adc_ch_data_d5 = 'd0;
reg [255:0] adc_ch_data_d6 = 'd0;
reg [255:0] adc_ch_data_d7 = 'd0;
reg adc_ch_valid_0 = 'd0;
reg adc_ch_valid_1 = 'd0;
reg adc_ch_valid_2 = 'd0;
reg adc_ch_valid_3 = 'd0;
reg adc_ch_valid_4 = 'd0;
reg adc_ch_valid_5 = 'd0;
reg adc_ch_valid_6 = 'd0;
reg adc_ch_valid_7 = 'd0;
reg [ 31:0] adc_ch_data_0 = 'd0;
reg [ 31:0] adc_ch_data_1 = 'd0;
reg [ 31:0] adc_ch_data_2 = 'd0;
reg [ 31:0] adc_ch_data_3 = 'd0;
reg [ 31:0] adc_ch_data_4 = 'd0;
reg [ 31:0] adc_ch_data_5 = 'd0;
reg [ 31:0] adc_ch_data_6 = 'd0;
reg [ 31:0] adc_ch_data_7 = 'd0;
reg adc_ch_valid = 'd0;
reg [255:0] adc_ch_data = 'd0;
reg [ 8:0] adc_cnt_p = 'd0;
reg adc_valid_p = 'd0;
reg [255:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_d1 = 'd0;
reg [ 7:0] adc_data_d2 = 'd0;
reg adc_ready_d1 = 'd0;
reg adc_ready = 'd0;
reg adc_ready_d = 'd0;
reg adc_sshot_m1 = 'd0;
reg adc_sshot = 'd0;
reg [ 1:0] adc_format_m1 = 'd0;
reg [ 1:0] adc_format = 'd0;
reg adc_crc_enable_m1 = 'd0;
reg adc_crc_enable = 'd0;
reg adc_crc_4_or_16_n_m1 = 'd0;
reg adc_crc_4_or_16_n = 'd0;
reg [ 35:0] adc_status_clr_m1 = 'd0;
reg [ 35:0] adc_status_clr = 'd0;
reg [ 35:0] adc_status_clr_d = 'd0;
// internal signals
wire [ 7:0] adc_crc_in_s;
wire [ 7:0] adc_crc_s;
wire adc_crc_mismatch_s;
wire adc_seq_fmatch_s;
wire adc_seq_fupdate_s;
wire [ 7:0] adc_enable_8_s;
wire [ 23:0] adc_seq_8_s;
wire adc_cnt_enable_1_s;
wire adc_cnt_enable_4_s;
wire adc_cnt_enable_8_s;
wire adc_cnt_enable_s;
wire [ 7:0] adc_data_in_s;
wire adc_ready_in_s;
wire adc_clk_in_s;
wire [ 35:0] adc_status_clr_s;
// function (crc)
function [ 7:0] crc8;
input [23:0] din;
input [ 7:0] cin;
reg [ 7:0] cout;
begin
cout[ 7] = cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 6] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^
din[13] ^ din[15] ^ din[17] ^ din[18] ^ din[20] ^ din[22];
cout[ 6] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 5] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^
din[12] ^ din[14] ^ din[16] ^ din[17] ^ din[19] ^ din[21];
cout[ 5] = cin[ 0] ^ cin[ 2] ^ cin[ 4] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^
din[13] ^ din[15] ^ din[16] ^ din[18] ^ din[20];
cout[ 4] = cin[ 1] ^ cin[ 3] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^
din[14] ^ din[15] ^ din[17] ^ din[19];
cout[ 3] = cin[ 0] ^ cin[ 2] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^
din[11] ^ din[13] ^ din[14] ^ din[16] ^ din[18] ^ din[23];
cout[ 2] = cin[ 1] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^
din[12] ^ din[13] ^ din[15] ^ din[17] ^ din[22];
cout[ 1] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ cin[ 7] ^ din[ 0] ^
din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23];
cout[ 0] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ cin[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^
din[ 8] ^ din[12] ^ din[14] ^ din[16] ^ din[18] ^ din[19] ^ din[21] ^ din[23];
crc8 = cout;
end
endfunction
// status
assign up_status[35:32] = {2'd0, adc_status_8};
assign up_status[31:28] = {1'd0, adc_status_7};
assign up_status[27:24] = {1'd0, adc_status_6};
assign up_status[23:20] = {1'd0, adc_status_5};
assign up_status[19:16] = {1'd0, adc_status_4};
assign up_status[15:12] = {1'd0, adc_status_3};
assign up_status[11: 8] = {1'd0, adc_status_2};
assign up_status[ 7: 4] = {1'd0, adc_status_1};
assign up_status[ 3: 0] = {1'd0, adc_status_0};
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_status_8 <= adc_status_8 | adc_status[1:0];
end else begin
adc_status_8 <= adc_status_8 & ~adc_status_clr_s[33:32];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd7)) begin
adc_status_7 <= adc_status_7 | adc_status[4:2];
end else begin
adc_status_7 <= adc_status_7 & ~adc_status_clr_s[30:28];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd6)) begin
adc_status_6 <= adc_status_6 | adc_status[4:2];
end else begin
adc_status_6 <= adc_status_6 & ~adc_status_clr_s[26:24];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd5)) begin
adc_status_5 <= adc_status_5 | adc_status[4:2];
end else begin
adc_status_5 <= adc_status_5 & ~adc_status_clr_s[22:20];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd4)) begin
adc_status_4 <= adc_status_4 | adc_status[4:2];
end else begin
adc_status_4 <= adc_status_4 & ~adc_status_clr_s[18:16];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd3)) begin
adc_status_3 <= adc_status_3 | adc_status[4:2];
end else begin
adc_status_3 <= adc_status_3 & ~adc_status_clr_s[14:12];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd2)) begin
adc_status_2 <= adc_status_2 | adc_status[4:2];
end else begin
adc_status_2 <= adc_status_2 & ~adc_status_clr_s[10: 8];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd1)) begin
adc_status_1 <= adc_status_1 | adc_status[4:2];
end else begin
adc_status_1 <= adc_status_1 & ~adc_status_clr_s[ 6: 4];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd0)) begin
adc_status_0 <= adc_status_0 | adc_status[4:2];
end else begin
adc_status_0 <= adc_status_0 & ~adc_status_clr_s[ 2: 0];
end
end
// data & status
always @(posedge adc_clk) begin
adc_valid <= adc_valid_int & adc_enable_int;
adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]};
adc_seq <= adc_seq_int;
if ((adc_crc_enable == 1'b1) && (adc_crc_scnt_int == 4'd0)) begin
adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
adc_status[3] <= 1'b0;
adc_status[2] <= 1'b0;
adc_status[1] <= 1'b0;
adc_status[0] <= adc_seq_foos;
end else begin
adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
adc_status[3] <= adc_data_int[30] & adc_enable_int;
adc_status[2] <= adc_data_int[27] & adc_enable_int;
adc_status[1] <= adc_data_int[31] & adc_enable_int;
adc_status[0] <= adc_seq_foos;
end
end
// crc- not much useful at the interface, since it is post-framing
assign adc_crc_in_s = (adc_crc_scnt_int == 4'd1) ? 8'hff : adc_crc_8[63:56];
assign adc_crc_s = crc8(adc_data_int[23:0], adc_crc_in_s);
assign adc_crc_mismatch_s = (adc_crc_data == adc_crc_8[7:0]) ? 1'b0 : adc_crc_enable;
always @(posedge adc_clk) begin
if (adc_valid_int == 1'b1) begin
adc_crc_8 <= {adc_crc_8[55:0], adc_crc_s};
end
if (adc_valid_int == 1'b1) begin
adc_crc_mismatch_int <= {adc_crc_mismatch_int[6:0], 1'd0};
end else begin
adc_crc_mismatch_int <= adc_crc_mismatch_8;
end
if (adc_crc_scnt_int == 4'd0) begin
adc_crc_valid <= adc_valid_int;
end else begin
adc_crc_valid <= 1'd0;
end
adc_crc_data <= adc_data_int[31:24];
if (adc_crc_valid == 1'b1) begin
adc_crc_mismatch_8 <= {adc_crc_mismatch_8[6:0], adc_crc_mismatch_s};
end
end
// data interleaved & all-aligned
always @(posedge adc_clk) begin
adc_valid_int <= adc_valid_8;
adc_data_int <= adc_data_8;
adc_seq_int <= adc_seq_8[23:21];
adc_enable_int <= adc_enable_8[7] & adc_valid_8;
adc_crc_scnt_int <= adc_crc_scnt_8;
end
// crc- count
always @(posedge adc_clk) begin
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
if (adc_seq_fmatch_s == 1'b0) begin
adc_crc_scnt_8 <= 4'd1;
end else if ((adc_crc_4_or_16_n == 1'b1) && (adc_crc_scnt_8 == 4'h3)) begin
adc_crc_scnt_8 <= 4'd0;
end else begin
adc_crc_scnt_8 <= adc_crc_scnt_8 + 1'b1;
end
end
end
// three sample framing logic
always @(posedge adc_clk) begin
if (adc_ready == 1'b0) begin
adc_seq_data <= 24'd0;
end else if (adc_valid_8 == 1'b1) begin
adc_seq_data <= {adc_seq_data[20:0], adc_data_8[26:24]};
end
end
assign adc_seq_fmatch_s = (adc_seq_data == adc_seq_fdata) ? 1'b1 : 1'b0;
assign adc_seq_fupdate_s = adc_seq_fmatch_s ^ adc_seq_fmatch;
always @(posedge adc_clk) begin
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
adc_seq_fmatch <= adc_seq_fmatch_s;
if (adc_seq_foos == 1'b1) begin
adc_seq_fdata <= adc_seq_data;
end
if (adc_seq_fupdate_s == 1'b0) begin
adc_seq_foos <= ~adc_seq_fmatch_s;
end
end
end
// we are cluless on 0 -- safe to compare all 32bits against 0x0?
assign adc_enable_8_s[7] = (adc_seq_8[23:21] == adc_seq_fdata[23:21]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[6] = (adc_seq_8[20:18] == adc_seq_fdata[20:18]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[5] = (adc_seq_8[17:15] == adc_seq_fdata[17:15]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[4] = (adc_seq_8[14:12] == adc_seq_fdata[14:12]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[3] = (adc_seq_8[11: 9] == adc_seq_fdata[11: 9]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[2] = (adc_seq_8[ 8: 6] == adc_seq_fdata[ 8: 6]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[1] = (adc_seq_8[ 5: 3] == adc_seq_fdata[ 5: 3]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[0] = (adc_seq_8[ 2: 0] == adc_seq_fdata[ 2: 0]) ? 1'b1 : 1'b0;
always @(posedge adc_clk) begin
if (adc_ready_d == 1'b0) begin
adc_enable_8 <= adc_enable_8_s;
end else if (adc_valid_8 == 1'b1) begin
adc_enable_8 <= {adc_enable_8[6:0], 1'd0};
end
end
// channel-sequence
assign adc_seq_8_s[23:21] = (adc_format == 2'b01) ? 3'd0 : 3'd0;
assign adc_seq_8_s[20:18] = (adc_format == 2'b01) ? 3'd4 : 3'd1;
assign adc_seq_8_s[17:15] = (adc_format == 2'b01) ? 3'd1 : 3'd2;
assign adc_seq_8_s[14:12] = (adc_format == 2'b01) ? 3'd5 : 3'd3;
assign adc_seq_8_s[11: 9] = (adc_format == 2'b01) ? 3'd2 : 3'd4;
assign adc_seq_8_s[ 8: 6] = (adc_format == 2'b01) ? 3'd6 : 3'd5;
assign adc_seq_8_s[ 5: 3] = (adc_format == 2'b01) ? 3'd3 : 3'd6;
assign adc_seq_8_s[ 2: 0] = (adc_format == 2'b01) ? 3'd7 : 3'd7;
always @(posedge adc_clk) begin
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
adc_seq_8 <= adc_seq_8_s;
end else if (adc_valid_8 == 1'b1) begin
adc_seq_8 <= {adc_seq_8[20:0], 3'd0};
end
end
// data (interleaving)
always @(posedge adc_clk) begin
adc_valid_8 <= adc_ch_valid_0 | adc_ch_valid_1 | adc_ch_valid_2 | adc_ch_valid_3 |
adc_ch_valid_4 | adc_ch_valid_5 | adc_ch_valid_6 | adc_ch_valid_7;
adc_data_8 <= adc_ch_data_0 | adc_ch_data_1 | adc_ch_data_2 | adc_ch_data_3 |
adc_ch_data_4 | adc_ch_data_5 | adc_ch_data_6 | adc_ch_data_7;
end
always @(posedge adc_clk) begin
adc_ch_valid_d <= {adc_ch_valid_d[6:0], adc_ch_valid};
adc_ch_data_d0[((32*0)+31):(32*0)] <= adc_ch_data[((32*0)+31):(32*0)];
adc_ch_data_d0[((32*7)+31):(32*1)] <= adc_ch_data_d0[((32*6)+31):(32*0)];
adc_ch_data_d1[((32*0)+31):(32*0)] <= adc_ch_data[((32*1)+31):(32*1)];
adc_ch_data_d1[((32*7)+31):(32*1)] <= adc_ch_data_d1[((32*6)+31):(32*0)];
adc_ch_data_d2[((32*0)+31):(32*0)] <= adc_ch_data[((32*2)+31):(32*2)];
adc_ch_data_d2[((32*7)+31):(32*1)] <= adc_ch_data_d2[((32*6)+31):(32*0)];
adc_ch_data_d3[((32*0)+31):(32*0)] <= adc_ch_data[((32*3)+31):(32*3)];
adc_ch_data_d3[((32*7)+31):(32*1)] <= adc_ch_data_d3[((32*6)+31):(32*0)];
adc_ch_data_d4[((32*0)+31):(32*0)] <= adc_ch_data[((32*4)+31):(32*4)];
adc_ch_data_d4[((32*7)+31):(32*1)] <= adc_ch_data_d4[((32*6)+31):(32*0)];
adc_ch_data_d5[((32*0)+31):(32*0)] <= adc_ch_data[((32*5)+31):(32*5)];
adc_ch_data_d5[((32*7)+31):(32*1)] <= adc_ch_data_d5[((32*6)+31):(32*0)];
adc_ch_data_d6[((32*0)+31):(32*0)] <= adc_ch_data[((32*6)+31):(32*6)];
adc_ch_data_d6[((32*7)+31):(32*1)] <= adc_ch_data_d6[((32*6)+31):(32*0)];
adc_ch_data_d7[((32*0)+31):(32*0)] <= adc_ch_data[((32*7)+31):(32*7)];
adc_ch_data_d7[((32*7)+31):(32*1)] <= adc_ch_data_d7[((32*6)+31):(32*0)];
end
always @(posedge adc_clk) begin
adc_ch_valid_0 <= adc_ch_valid_d[0];
adc_ch_valid_1 <= adc_ch_valid_d[1] & ~adc_format[1];
adc_ch_valid_2 <= adc_ch_valid_d[2] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_3 <= adc_ch_valid_d[3] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_4 <= adc_ch_valid_d[4] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_5 <= adc_ch_valid_d[5] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_6 <= adc_ch_valid_d[6] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_7 <= adc_ch_valid_d[7] & ~adc_format[1] & ~adc_format[0];
adc_ch_data_0 <= adc_ch_data_d0[((32*0)+31):(32*0)];
adc_ch_data_1 <= adc_ch_data_d1[((32*1)+31):(32*1)];
adc_ch_data_2 <= adc_ch_data_d2[((32*2)+31):(32*2)];
adc_ch_data_3 <= adc_ch_data_d3[((32*3)+31):(32*3)];
adc_ch_data_4 <= adc_ch_data_d4[((32*4)+31):(32*4)];
adc_ch_data_5 <= adc_ch_data_d5[((32*5)+31):(32*5)];
adc_ch_data_6 <= adc_ch_data_d6[((32*6)+31):(32*6)];
adc_ch_data_7 <= adc_ch_data_d7[((32*7)+31):(32*7)];
end
always @(posedge adc_clk) begin
adc_ch_valid <= adc_valid_p;
if (adc_valid_p == 1'b1) begin
adc_ch_data <= adc_data_p;
end else begin
adc_ch_data <= 256'd0;
end
end
// data (common)
assign adc_cnt_enable_1_s = (adc_cnt_p <= 9'h01f) ? 1'b1 : 1'b0;
assign adc_cnt_enable_4_s = (adc_cnt_p <= 9'h07f) ? 1'b1 : 1'b0;
assign adc_cnt_enable_8_s = (adc_cnt_p <= 9'h0ff) ? 1'b1 : 1'b0;
assign adc_cnt_enable_s = (adc_format == 2'b00) ? adc_cnt_enable_1_s :
((adc_format == 2'b01) ? adc_cnt_enable_4_s : adc_cnt_enable_8_s);
always @(posedge adc_clk) begin
if (adc_ready == 1'b0) begin
adc_cnt_p <= 9'h000;
end else if (adc_cnt_enable_s == 1'b1) begin
adc_cnt_p <= adc_cnt_p + 1'b1;
end
if (adc_cnt_p[4:0] == 5'h1f) begin
adc_valid_p <= 1'b1;
end else begin
adc_valid_p <= 1'b0;
end
end
// data (individual lanes)
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_data
always @(posedge adc_clk) begin
if (adc_cnt_p[4:0] == 5'h00) begin
adc_data_p[((32*n)+31):(32*n)] <= {31'd0, adc_data_d2[n]};
end else begin
adc_data_p[((32*n)+31):(32*n)] <= {adc_data_p[((32*n)+30):(32*n)], adc_data_d2[n]};
end
end
always @(posedge adc_clk) begin
adc_data_d1[n] <= adc_data_in_s[n];
adc_data_d2[n] <= adc_data_d1[n];
end
IBUF i_ibuf_data (
.I (data_in[n]),
.O (adc_data_in_s[n]));
end
endgenerate
// ready (single shot or continous)
always @(posedge adc_clk) begin
adc_ready_d1 <= adc_ready_in_s;
adc_ready <= adc_sshot ~^ adc_ready_d1;
adc_ready_d <= adc_ready;
end
IBUF i_ibuf_ready (
.I (ready_in),
.O (adc_ready_in_s));
// clock (use bufg delay ~4ns on 29ns)
BUFG i_bufg_clk (
.I (adc_clk_in_s),
.O (adc_clk));
IBUFG i_ibufg_clk (
.I (clk_in),
.O (adc_clk_in_s));
// control signals
assign adc_status_clr_s = adc_status_clr & ~adc_status_clr_d;
always @(posedge adc_clk) begin
adc_sshot_m1 <= up_sshot;
adc_sshot <= adc_sshot_m1;
adc_format_m1 <= up_format;
adc_format <= adc_format_m1;
adc_crc_enable_m1 <= up_crc_enable;
adc_crc_enable <= adc_crc_enable_m1;
adc_crc_4_or_16_n_m1 <= up_crc_4_or_16_n;
adc_crc_4_or_16_n <= adc_crc_4_or_16_n_m1;
adc_status_clr_m1 <= up_status_clr;
adc_status_clr <= adc_status_clr_m1;
adc_status_clr_d <= adc_status_clr;
end
endmodule
// ***************************************************************************
// ***************************************************************************

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# ad7768 interface
create_bd_port -dir I adc_clk
create_bd_port -dir I adc_valid
create_bd_port -dir I -from 31 -to 0 adc_data
create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t
create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t
# instances
ad_ip_instance axi_dmac ad7768_dma
ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter ad7768_dma CONFIG.CYCLIC 0
ad_ip_parameter ad7768_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter ad7768_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter ad7768_dma CONFIG.DMA_DATA_WIDTH_SRC 32
# ps7-hp1
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1
# gpio
ad_ip_instance axi_gpio ad7768_gpio
ad_ip_parameter ad7768_gpio CONFIG.C_IS_DUAL 1
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO2_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1
# interconnects
ad_connect adc_clk ad7768_dma/fifo_wr_clk
ad_connect adc_valid ad7768_dma/fifo_wr_en
ad_connect adc_data ad7768_dma/fifo_wr_din
ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i
ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o
ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t
ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i
ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o
ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t
# interrupts
ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq
ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt
# cpu / memory interconnects
ad_cpu_interconnect 0x7C400000 ad7768_dma
ad_cpu_interconnect 0x7C420000 ad7768_gpio
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma/m_dest_axi

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7768evb_zed
M_DEPS += ../common/ad7768evb_bd.tcl
M_DEPS += ../common/ad7768_if.v
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_i2c_mixer
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad7768evb_bd.tcl

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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports clk_in] ; ## H04 FMC_LPC_CLK0_M2C_P IO_L12P_T1_MRCC_34
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ready_in] ; ## G06 FMC_LPC_LA00_CC_P IO_L13P_T2_MRCC_34
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports data_in[0]] ; ## G07 FMC_LPC_LA00_CC_N IO_L13N_T2_MRCC_34
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports data_in[1]] ; ## C11 FMC_LPC_LA06_N IO_L10N_T1_34
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports data_in[2]] ; ## H07 FMC_LPC_LA02_P IO_L20P_T3_34
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports data_in[3]] ; ## H08 FMC_LPC_LA02_N IO_L20N_T3_34
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports data_in[4]] ; ## G12 FMC_LPC_LA08_P IO_L8P_T1_34
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports data_in[5]] ; ## G13 FMC_LPC_LA08_N IO_L8N_T1_34
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports data_in[6]] ; ## D14 FMC_LPC_LA09_P IO_L17P_T2_34
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports data_in[7]] ; ## D15 FMC_LPC_LA09_N IO_L17N_T2_34
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D11 FMC_LPC_LA05_P IO_L7P_T1_34
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D08 FMC_LPC_LA01_CC_P IO_L14P_T2_SRCC_34
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H11 FMC_LPC_LA04_N IO_L15N_T2_DQS_34
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G09 FMC_LPC_LA03_P IO_L16P_T2_34
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gpio_0_mode_0] ; ## C15 FMC_LPC_LA10_N IO_L22N_T3_34
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_1_mode_1] ; ## H13 FMC_LPC_LA07_P IO_L21P_T3_DQS_34
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_2_mode_2] ; ## H14 FMC_LPC_LA07_N IO_L21N_T3_DQS_34
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_3_mode_3] ; ## H16 FMC_LPC_LA11_P IO_L5P_T0_34
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_4_filter] ; ## C14 FMC_LPC_LA10_P IO_L22P_T3_34
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports reset_n] ; ## C10 FMC_LPC_LA06_P IO_L10P_T1_34
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports start_n] ; ## G10 FMC_LPC_LA03_N IO_L16N_T2_34
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports sync_n] ; ## H10 FMC_LPC_LA04_P IO_L15P_T2_DQS_34
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports sync_in_n] ; ## D12 FMC_LPC_LA05_N IO_L7N_T1_34
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports mclk] ; ## D09 FMC_LPC_LA01_CC_N IO_L14N_T2_SRCC_34
create_clock -name adc_clk -period 20 [get_ports clk_in]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx ad7768evb_zed
adi_project_files ad7768evb_zed [list \
"../common/ad7768_if.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ]
adi_project_run ad7768evb_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
input clk_in,
input ready_in,
input [ 7:0] data_in,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso,
inout gpio_0_mode_0,
inout gpio_1_mode_1,
inout gpio_2_mode_2,
inout gpio_3_mode_3,
inout gpio_4_filter,
inout reset_n,
inout start_n,
inout sync_n,
inout sync_in_n,
output mclk);
// internal signals
wire adc_clk;
wire adc_valid;
wire [31:0] adc_data;
wire up_sshot;
wire [ 1:0] up_format;
wire up_crc_enable;
wire up_crc_4_or_16_n;
wire [63:0] adc_gpio_i;
wire [63:0] adc_gpio_o;
wire [63:0] adc_gpio_t;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// use crystal
assign mclk = 1'b0;
assign up_sshot = gpio_o[36];
assign up_format = gpio_o[35:34];
assign up_crc_enable = gpio_o[33];
assign up_crc_4_or_16_n = gpio_o[32];
// instantiations
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
.dio_t ({gpio_t[52:48], gpio_t[43:40]}),
.dio_i ({gpio_o[52:48], gpio_o[43:40]}),
.dio_o ({gpio_i[52:48], gpio_i[43:40]}),
.dio_p ({ gpio_4_filter, // 52
gpio_3_mode_3, // 51
gpio_2_mode_2, // 50
gpio_1_mode_1, // 49
gpio_0_mode_0, // 48
sync_in_n, // 43
sync_n, // 42
start_n, // 41
reset_n})); // 40
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
.dio_p (gpio_bd));
assign gpio_i[36:32] = 5'b0;
assign gpio_i[39:37] = gpio_o[39:37];
assign gpio_i[47:44] = gpio_o[47:44];
assign gpio_i[63:53] = gpio_o[63:53];
ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_scl (
.dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_sda (
.dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
.dio_p (iic_mux_sda));
ad7768_if i_ad7768_if (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data (adc_data),
.up_sshot (up_sshot),
.up_format (up_format),
.up_crc_enable (up_crc_enable),
.up_crc_4_or_16_n (up_crc_4_or_16_n),
.up_status_clr (adc_gpio_o[32:0]),
.up_status (adc_gpio_i[32:0]));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_gpio_0_i (adc_gpio_i[31:0]),
.adc_gpio_0_o (adc_gpio_o[31:0]),
.adc_gpio_0_t (adc_gpio_t[31:0]),
.adc_gpio_1_i (adc_gpio_i[63:32]),
.adc_gpio_1_o (adc_gpio_o[63:32]),
.adc_gpio_1_t (adc_gpio_t[63:32]),
.adc_valid (adc_valid),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
# create a SPI Engine architecture
create_bd_cell -type hier spi
current_bd_instance /spi
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
ad_ip_instance spi_engine_execution execution
ad_ip_instance axi_spi_engine axi
ad_ip_instance spi_engine_offload offload
ad_ip_instance spi_engine_interconnect interconnect
ad_ip_instance util_pulse_gen trigger_gen
ad_ip_parameter offload CONFIG.DATA_WIDTH 16
ad_ip_parameter axi CONFIG.DATA_WIDTH 16
ad_ip_parameter interconnect CONFIG.DATA_WIDTH 16
ad_ip_parameter execution CONFIG.DATA_WIDTH 16
## to setup the sample rate of the system change the PULSE_PERIOD value
## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
set cycle_per_sec_100mhz 100000000
set sampling_cycle [expr int(ceil(double($cycle_per_sec_100mhz) / $adc_sampling_rate))]
ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle
ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1
ad_ip_parameter execution CONFIG.NUM_OF_CS 1
ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
ad_connect offload/offload_sdi M_AXIS_SAMPLE
ad_connect execution/spi m_spi
ad_connect clk offload/spi_clk
ad_connect clk offload/ctrl_clk
ad_connect clk execution/clk
ad_connect clk axi/s_axi_aclk
ad_connect clk axi/spi_clk
ad_connect clk interconnect/clk
ad_connect clk trigger_gen/clk
ad_connect axi/spi_resetn offload/spi_resetn
ad_connect axi/spi_resetn execution/resetn
ad_connect axi/spi_resetn interconnect/resetn
ad_connect axi/spi_resetn trigger_gen/rstn
ad_connect trigger_gen/pulse_period_en GND
ad_connect trigger_gen/pulse_period GND
ad_connect trigger_gen/pulse offload/trigger
ad_connect resetn axi/s_axi_aresetn
ad_connect irq axi/irq
current_bd_instance /
ad_ip_instance axi_dmac axi_adaq7980_dma
ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_adaq7980_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_adaq7980_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_adaq7980_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adaq7980_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect sys_cpu_clk spi/clk
ad_connect sys_cpu_resetn spi/resetn
ad_connect sys_cpu_resetn axi_adaq7980_dma/m_dest_axi_aresetn
ad_connect spi/m_spi spi
ad_connect axi_adaq7980_dma/s_axis spi/M_AXIS_SAMPLE
ad_cpu_interconnect 0x44a00000 spi/axi
ad_cpu_interconnect 0x44a30000 axi_adaq7980_dma
ad_connect sys_cpu_clk axi_adaq7980_dma/s_axis_aclk
ad_cpu_interrupt "ps-13" "mb-13" axi_adaq7980_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" spi/irq
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_adaq7980_dma/m_dest_axi

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := adaq7980_sdz_zed
M_DEPS += ../common/adaq7980_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pulse_gen
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
# specify ADC sampling rate in samples/seconds -- default is 1 MSPS
set adc_sampling_rate 1000000
source ../common/adaq7980_bd.tcl

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# SPI interface
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports spi_sdi] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA15_P
# GPIO signals
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[2]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[3]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[4]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[5]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[6]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[7]] ; ## FMC_LPC_LA27_N
# REF_PD and RBUF_PD
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports adaq7980_ref_pd] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports adaq7980_rbuf_pd] ; ## FMC_LPC_LA29_P

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx adaq7980_sdz_zed
adi_project_files adaq7980_sdz_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run adaq7980_sdz_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
input spi_sdi,
output spi_sclk,
output spi_cs,
inout [ 7:0] adaq7980_gpio,
inout adaq7980_rbuf_pd,
inout adaq7980_ref_pd);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_pd (
.dio_t(gpio_t[41:40]),
.dio_i(gpio_o[41:40]),
.dio_o(gpio_i[41:40]),
.dio_p({adaq7980_rbuf_pd, adaq7980_ref_pd}));
ad_iobuf #(
.DATA_WIDTH(8)
) i_iobuf_gpio (
.dio_t(gpio_t[39:32]),
.dio_i(gpio_o[39:32]),
.dio_o(gpio_i[39:32]),
.dio_p(adaq7980_gpio));
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spi_sdo (),
.spi_sdo_t (),
.spi_sdi (spi_sdi),
.spi_cs (spi_cs),
.spi_sclk (spi_sclk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************