diff --git a/projects/ad9082_fmca_ebz/zcu102/Makefile b/projects/ad9082_fmca_ebz/zcu102/Makefile new file mode 100644 index 000000000..37b494618 --- /dev/null +++ b/projects/ad9082_fmca_ebz/zcu102/Makefile @@ -0,0 +1,37 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9082_fmca_ebz_zcu102 + +M_DEPS += ../../ad9081_fmca_ebz/zcu102/timing_constr.xdc +M_DEPS += ../../ad9081_fmca_ebz/zcu102/system_constr.xdc +M_DEPS += ../../ad9081_fmca_ebz/zcu102/system_top.v +M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9082_fmca_ebz/zcu102/system_bd.tcl b/projects/ad9082_fmca_ebz/zcu102/system_bd.tcl new file mode 100644 index 000000000..3290d35c4 --- /dev/null +++ b/projects/ad9082_fmca_ebz/zcu102/system_bd.tcl @@ -0,0 +1,57 @@ + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr 64*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr 64*1024] + + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0 + +source ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Parameters for 15.5Gpbs lane rate + +ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 +ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868 +ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3 + +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF + + diff --git a/projects/ad9082_fmca_ebz/zcu102/system_project.tcl b/projects/ad9082_fmca_ebz/zcu102/system_project.tcl new file mode 100644 index 000000000..7c61686ea --- /dev/null +++ b/projects/ad9082_fmca_ebz/zcu102/system_project.tcl @@ -0,0 +1,62 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# +# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode +# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode +# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode +# Encoding is: +# 0 - CPLL +# 1 - QPLL0 +# 2 - QPLL1 +# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported +# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices +# +# +# !!! For this carrier only 8B10B mode is supported !!! +# + +adi_project ad9082_fmca_ebz_zcu102 0 [list \ + JESD_MODE 8B10B \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ +] + +adi_project_files ad9082_fmca_ebz_zcu102 [list \ + "../../ad9081_fmca_ebz/zcu102/system_top.v" \ + "../../ad9081_fmca_ebz/zcu102/system_constr.xdc" \ + "../../ad9081_fmca_ebz/zcu102/timing_constr.xdc" \ + "../../../library/common/ad_3w_spi.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + + +adi_project_run ad9082_fmca_ebz_zcu102 +